Gate Dielectric Thickness Layout for FinFET and GAA Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down gate stacks for input/output (I/O) and core devices with varying gate dielectric layer thicknesses, as existing GAA transistors are not suitable for applications requiring thick gate dielectric layers, and different applications prefer different thicknesses for leakage and speed performance.
Innovation Solution
The integration of FinFET and GAA transistors with varying gate dielectric layer thicknesses on the same substrate, where FinFETs in the I/O area have a thicker gate dielectric layer for high-voltage applications, and GAA transistors in the core area have thinner layers for high-speed or low-leakage applications, allowing for flexible design integration schemes that accommodate different circuits within the same IC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If GAA transistors are used with thin gate dielectric layers, then high-speed performance is improved, but they are not suitable for high-voltage I/O applications requiring thick gate dielectric layers
Solution Approach 1:
The patent divides the semiconductor device into distinct first and second device areas, each containing transistors with different gate dielectric layer thicknesses. The first area contains transistors with thinner gate dielectric layers optimized for high-speed core logic, while the second area contains transistors with thicker gate dielectric layers optimized for high-voltage I/O applications. This spatial segmentation allows each region to be independently optimized for its specific functional requirements.
Solution Approach 2:
The patent implements local quality by providing different gate dielectric layer thicknesses in different spatial locations on the same substrate. The gate dielectric layer thickness is locally optimized: thinner in the first device area for high-speed performance and thicker in the second device area for high-voltage tolerance. This enables each local region to have the specific properties needed for its intended application.
2Reliability
If different gate dielectric layer thicknesses are used for different applications, then performance is optimized, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary action by forming a thickness modulation layer before depositing the gate dielectric material. This thickness modulation layer is patterned with different thicknesses in different areas (thinner in the first device area, thicker in the second device area). When the gate dielectric layer is deposited conformally over this modulation layer, the preliminary thickness variation is transferred to the final gate dielectric structure, enabling different effective thicknesses without requiring separate deposition processes for each area.
Solution Approach 2:
The thickness modulation layer serves as an intermediary structure that enables the creation of different gate dielectric layer thicknesses. Rather than directly forming different thicknesses through complex process control, the modulation layer acts as a template or mediator that defines the desired thickness profile. This intermediary approach simplifies the overall manufacturing process by decoupling the thickness definition step from the dielectric deposition step.
Data Source
AI summary
A method includes forming a first channel region, a second channel region, and a third channel region over a substrate, depositing a first interfacial layer over the first, second, and third channel regions, removing the first interfacial layer from the first and second channel regions, depositing a second interfacial layer over the first and second channel regions, thinning a thickness of the second interfacial layer over the first channel region, depositing a high-k dielectric layer over the first, second, and third channel regions, and forming a gate electrode layer over the first, second, and third channel regions.