Varying Gate Dielectric Thickness in FinFET and GAA Transistors
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down gate stacks for input/output (I/O) and core devices with varying gate dielectric layer thicknesses, as existing GAA transistors are not suitable for applications requiring thick gate dielectric layers, and different core functions prefer different thicknesses for high-speed and low-power applications.
Innovation Solution
The integration of FinFET and GAA transistors with varying gate dielectric layer thicknesses on the same substrate, where FinFETs in the I/O area have a thicker gate dielectric layer for high-voltage applications, and GAA transistors in the core area have thinner layers for high-speed and low-power applications, allowing for flexible design integration and existing manufacturing flow compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If GAA transistors are used with thin gate dielectric layers for high-speed applications, then speed performance is improved, but leakage control deteriorates
Solution Approach 1:
The patent applies local quality by implementing different gate dielectric layer thicknesses in different regions of the same semiconductor device. Specifically, the gate dielectric layer has a first thickness in the I/O region and a second thickness (different from the first) in the core logic region, allowing each region to be optimized for its specific function while using the same GAA transistor structure
2Loss of energy
If thick gate dielectric layers are used for I/O devices, then leakage is reduced, but high-speed performance deteriorates
Solution Approach 1:
The patent implements local quality by spatially varying the gate dielectric layer thickness across different functional regions. The I/O region receives a thicker gate dielectric layer for leakage suppression, while the core logic region receives a thinner layer for high-speed performance, with the transition managed through selective epitaxial growth and etching processes
3Adaptability or versatility
If varying gate dielectric layer thicknesses are implemented for different applications, then device versatility is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor substrate into distinct functional regions (I/O region and core logic region) and applying different gate dielectric layer thicknesses to each region. This is achieved through selective epitaxial growth followed by region-specific etching processes, allowing independent optimization of each region while maintaining a unified manufacturing flow
Solution Approach 2:
The patent uses an intermediary approach by implementing a uniform gate dielectric layer initially through selective epitaxial growth, then using selective etching as an intermediary process to create the desired thickness variation. This intermediary step allows the system to maintain process simplicity while achieving the complex thickness profile needed for multi-application optimization
Data Source
AI summary
A semiconductor device includes a substrate having a first region and a second region. Multiple nanostructures are vertically stacked above the first region of the substrate. A first gate dielectric layer wraps each of the nanostructures. A first gate electrode layer is disposed on the first gate dielectric layer. A fin protruding from the second region of the substrate. The fin includes alternating first and second semiconductor layers with different material compositions. A second gate dielectric layer is disposed on top and sidewall surfaces of the fin. A second gate electrode layer is disposed on the second gate dielectric layer. A thickness of the first gate dielectric layer is smaller than a thickness of the second gate dielectric layer.