Gate Dielectric Thickness Tuning in Embedded FinFET and GAA Gates
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Solution Overview
Problem
The challenge in the semiconductor industry is to form reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, requiring innovative methods to improve processing efficiency and reliability.
Innovation Solution
The solution involves forming semiconductor device structures with FinFETs and gate all around (GAA) transistors using advanced patterning techniques like double-patterning or multi-patterning processes, and employing atomic layer deposition (ALD) to create gate dielectric layers with varying thicknesses in different trenches, allowing for improved transistor performance by adjusting chemisorption forces of ALD precursors and deposition rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication processes become more difficult and reliability decreases
Solution Approach 1:
The fabrication process is divided into multiple sequential stages: forming mandrels at a first pitch, depositing spacers, selectively removing mandrels, and forming features at a second (smaller) pitch. This segmentation allows complex small-features fabrication to be broken into manageable steps, improving reliability while achieving high functional density
Solution Approach 2:
Mandrels are formed in advance as sacrificial structures to define the positions of subsequent features. The spacers are deposited beforehand to protect certain regions during selective removal. These preliminary actions enable precise control over final feature placement, ensuring fabrication reliability at scaled dimensions
2Productivity
If feature sizes decrease to increase functional density, then more devices fit per chip area, but the complexity of processing increases
Solution Approach 1:
The spacer structures self-align to the mandrels through conformal deposition, automatically defining their positions without requiring additional alignment steps. The selective removal process uses the spacers as self-defined masks, eliminating the need for separate photolithography patterns. This self-service mechanism reduces processing complexity while achieving high functional density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor devices with enhanced performance, including improved driving current, reduced leakage current, increased switching speed, and the ability to withstand high voltages, while simplifying the fabrication process and reducing costs by eliminating the need for additional photolithography and etching steps.
Implementation Method 1
adjusting chemisorption forces of ALD precursors and deposition rates
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes an insulating layer over the substrate. The semiconductor device structure includes a first gate structure and a second gate structure embedded in the insulating layer. The first gate structure is wider than the second gate structure, the first gate structure includes a first gate dielectric layer and a first gate electrode layer over the first gate dielectric layer, the second gate structure includes a second gate dielectric layer and a second gate electrode layer over the second gate dielectric layer, the first gate dielectric layer and the second gate dielectric layer are made of a same material, and the second gate dielectric layer is thinner than the first gate dielectric layer.