Gate Dielectric Thinning Reduction at Trench Isolation Edges
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Solution Overview
Problem
Conventional trench isolation methods in semiconductor manufacturing result in significant gate oxide thinning at trench/active area interfaces, leading to yield loss and reliability issues, especially for thicker gate oxides required in high-voltage transistors.
Innovation Solution
A method involving the deposition and complete oxidation of a polysilicon or amorphous silicon layer to form a thick gate dielectric, which extends over trench edges, reducing the need for thermally grown gate oxide and minimizing thinning, combined with standard semiconductor manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If thermally grown gate oxide is used for thick gate dielectric (300-5000 Angstroms), then high-voltage transistor performance is achieved, but significant gate oxide thinning occurs at trench isolation edges
Solution Approach 1:
A sacrificial gate oxide layer is grown thermally before trench isolation formation, and then selectively removed. This preliminary action creates a template that guides subsequent dielectric deposition, ensuring uniform thickness distribution including at trench edges where thinning would normally occur.
Solution Approach 2:
A deposited dielectric material serves as an intermediary layer between the sacrificial gate oxide removal and the final gate oxide formation. This intermediary layer fills the trench isolation regions and provides a foundation that prevents direct thermal oxidation at trench edges, thereby eliminating the thinning problem while allowing thick gate oxide to be formed elsewhere.
2Manufacturing precision
If steam oxidation, higher temperature, and high pressure oxidation are used to prevent thinning, then thinning is reduced for small target thickness (25-200 Angstroms), but the process becomes complex and energy-intensive
Solution Approach 1:
The harmful thermal oxidation process at trench edges is extracted and eliminated by removing the sacrificial gate oxide and replacing it with a deposited dielectric material. This extraction eliminates the need for complex oxidation process modifications while maintaining uniform gate oxide thickness.
Solution Approach 2:
The gate dielectric formation process transitions from purely thermal oxidation to a combination of physical vapor deposition and selective thermal oxidation. This parameter change in the deposition method allows uniform thick gate oxide formation without the need for complex oxidation process adjustments.
3Quantity of substance
If thick gate oxide (300-5000 Angstroms) is grown thermally, then high-voltage transistor requirements are met, but yield loss and reliability problems occur due to gate oxide thinning at trench edges
Solution Approach 1:
The sacrificial gate oxide is grown and removed before trench isolation completion, establishing a predetermined pattern that prevents future thinning issues. This preliminary action ensures that when the final gate oxide is formed, uniform thickness is achieved across all regions including trench edges, eliminating reliability concerns.
Solution Approach 2:
The deposited dielectric material acts as a mediator that replaces the sacrificial oxide in trench regions, preventing direct thermal oxidation at vulnerable edge locations. This intermediary structure ensures uniform gate oxide thickness and eliminates the thinning mechanism that causes reliability problems in high-voltage transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures a consistent and thick gate oxide thickness across the trench isolation active area edges, significantly reducing yield loss and reliability issues associated with gate oxide thinning, while maintaining high-voltage transistor performance.
Implementation Method 1
The first silicon comprising layer is then completely oxidized to convert the first silicon comprising layer to a silicon oxide layer
Implementation Method 2
the trenches are then refilled with a deposited dielectric material, such as oxide deposited using a high-density plasma chemical vapor deposition (HDP-CVD) process
Data Source
AI summary
A method of fabricating an integrated circuit (IC) including a plurality of MOS transistors and ICs therefrom include providing a substrate having a silicon including surface, and forming a plurality of dielectric filled trench isolation regions in the substrate, wherein the silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. A first silicon including layer is deposited, wherein the first silicon including extends from a surface of the trench isolation regions over the trench isolation active area edges to the silicon including surface. The first silicon including layer is completely oxidized to convert the first silicon layer to a silicon oxide layer, wherein the silicon oxide layer provides at least a portion of a gate dielectric for at least one of the plurality of MOS transistors. A patterned gate electrode layer is formed over the gate dielectric, wherein the patterned gate electrode layer extends over at least one of the trench isolation active area edges to the silicon including surface, and fabrication is then completed.