Gate Dielectric Void Filling in Semiconductor Trench Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor components shrink, defects like voids or seams in trench isolation regions lead to titanium nitride excursion and wordline to wordline crosstalk issues during the fabrication of dynamic random access memory devices.
Innovation Solution
A semiconductor device and fabrication method involving a semiconductor substrate with a gate trench and trench isolation region, where a conformal first gate dielectric layer fills voids in the trench isolation region, and an in-situ steam generation process grows a second gate dielectric layer, improving the quality of the gate dielectric layer and reducing titanium nitride excursion and crosstalk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the width of trench isolation region is reduced to accommodate smaller electronic components, then the miniaturization of semiconductor devices is achieved, but voids or seams are formed in the trench isolation region leading to titanium nitride excursion and wordline to wordline crosstalk
Solution Approach 1:
The gate dielectric layer is divided into multiple segments: a first gate dielectric layer deposited conformally to fill voids, and a second gate dielectric layer grown via ISSG process. This segmentation allows each layer to address specific defects, with the first layer filling voids and the second layer providing high-quality insulation, thereby resolving the reliability issue caused by miniaturization
Solution Approach 2:
The first gate dielectric layer is deposited in advance via atomic layer deposition (ALD) to conformally cover the trench isolation region and fill voids or seams before the main gate fabrication process. This preliminary action prevents titanium nitride excursion by sealing defects beforehand, addressing the reliability concern that arises from reduced trench isolation width
2Ease of manufacture
If conventional deposition methods are used for gate dielectric layer, then the fabrication process is simple, but voids in trench isolation region cause titanium nitride excursion and crosstalk
Solution Approach 1:
The first gate dielectric layer acts as an intermediary material deposited by atomic layer deposition (ALD) between the trench isolation region and the gate structure. This intermediary layer fills voids and seals defects, preventing titanium nitride from excusing into voids and causing crosstalk, while the subsequent ISSG-grown second gate dielectric layer provides the final high-quality insulation
Solution Approach 2:
The invention changes the deposition parameters and methods by using atomic layer deposition (ALD) for the first gate dielectric layer to achieve conformal coverage and void filling, followed by in-situ steam generation (ISSG) process for the second layer. These parameter changes ensure complete void filling and high-quality dielectric properties, eliminating titanium nitride excursion and crosstalk while maintaining fabrication feasibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces titanium nitride excursion and wordline to wordline crosstalk by enhancing the quality of the gate dielectric layer, improving the leakage properties and overall performance of the semiconductor device.
Implementation Method 1
A first gate dielectric layer conformally covers the sidewall of the active area and the sidewall of the trench isolation region. The void in the sidewall of the trench isolation region is filled with the first gate dielectric layer
Implementation Method 2
An in-situ steam generation (ISSG) process is then performed to thermally grow a second gate dielectric layer on the sidewall of the active area
Implementation Method 3
An in-situ steam generation (ISSG) process is then performed to thermally grow a second gate dielectric layer on the sidewall of the active area
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a gate trench penetrating through an active area and a trench isolation region surrounding the active area. The gate trench exposes a sidewall of the active area and a sidewall of the trench isolation region. The sidewall of the trench isolation region includes a void. A first gate dielectric layer conformally covers the sidewall of the active area and the sidewall of the trench isolation region. The void in the sidewall of the trench isolation region is filled with the first gate dielectric layer. A second gate dielectric layer is grown on the sidewall of the active area. A gate is embedded in the gate trench.