Gate Dielectric Structure for Power-Logic Voltage Integration

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Solution Overview

Problem

Existing semiconductor devices face challenges in integrating power and logic components with different operating voltages without compromising manufacturing process stability or device performance.

Innovation Solution

The semiconductor device features a first gate dielectric layer with a first portion in contact with the substrate and a second portion protruding from the first portion, where the thickness of the first portion is smaller than the second gate dielectric layer, and the top surface of the second portion is at the same level as the second gate dielectric layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If gate dielectric layers of different thicknesses are formed for power components with different operating voltages, then device performance is improved, but manufacturing process complexity and feasibility deteriorate

Engineering Contradiction:
Improvedevice performanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by forming a first gate dielectric layer with a first thickness for the first power component and a second gate dielectric layer with a second thickness for the second power component, where the thicknesses are locally optimized according to different operating voltage requirements. This allows each component to have the appropriate dielectric thickness for its specific performance needs while maintaining overall manufacturing feasibility through a unified process flow.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If gate dielectric layers of the same thickness are formed for manufacturing simplicity, then manufacturing process stability is improved, but device performance is sacrificed

Engineering Contradiction:
Improvemanufacturing process stabilityVSAvoiddevice performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent resolves this contradiction by implementing local quality optimization where the first gate dielectric layer has a first thickness suited for the first power component's operating voltage, and the second gate dielectric layer has a second thickness suited for the second power component's operating voltage. This is achieved through a manufacturable process that forms different thicknesses in different regions while maintaining process stability.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If power components and logic components with different operating voltages are integrated, then device versatility is improved, but manufacturing process feasibility deteriorates

Engineering Contradiction:
Improvedevice versatilityVSAvoidmanufacturing process feasibility
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent enables integration of power components and logic components with different operating voltages by applying local quality principles. The first power component receives a first gate dielectric layer with a first thickness, the second power component receives a second gate dielectric layer with a second thickness, and logic components can receive appropriate dielectric layers, all within a unified manufacturing process that maintains feasibility while achieving versatility.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250204028A1Semiconductor device and method for forming the same
Publication Date: 2025.06.19 POWERCHIP SEMICON MFG CORP
  • US20250204028A1 patent drawing
  • US20250204028A1 patent drawing
  • US20250204028A1 patent drawing

AI summary

The present disclosure provides a semiconductor device and a method for forming the same. The semiconductor device includes a substrate including a first and a second active regions defined by a device isolation structure and first and second elements respectively disposed in the first and second active regions and respectively including a first and a second gate structures. The first gate structure includes a first gate electrode and a first gate dielectric layer between the substrate and the first gate electrode. The second gate structure includes a second gate electrode and a second gate dielectric layer between the substrate and the second gate electrode. The first gate dielectric layer includes a first portion in contact with the substrate and a second portion protruding from the first portion in a vertical direction, and the thickness of the first portion is smaller than that of the second gate dielectric layer.