Semiconductor Gate Diffusion Barrier for Impurity Control
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Solution Overview
Problem
The dual poly gate semiconductor fabrication process faces issues with impurity diffusion during heat treatment, leading to performance deterioration of transistors, as implanted impurities spread into adjacent regions.
Innovation Solution
A semiconductor device and method that incorporate a diffusion barrier portion between impurity doped portions in the gate layer, preventing impurity diffusion and maintaining transistor performance by adjusting the N-P space and using independent mask processes for forming impurity doped regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dual polysilicon gate is used to match work functions of NMOS and PMOS transistors, then transistor performance is improved, but implanted impurities diffuse into adjacent regions during heat treatment causing performance deterioration
Solution Approach 1:
The gate layer is segmented into three distinct regions: a first impurity-doped portion over the NMOS active region, a second impurity-doped portion over the PMOS active region, and an undoped portion positioned between them. This segmentation prevents the diffusion of opposite-type impurities into adjacent regions during heat treatment, while still maintaining the dual polysilicon gate structure needed for work function matching.
Solution Approach 2:
The undoped portion of the gate layer acts as an intermediary barrier between the first and second impurity-doped portions. This intermediate region prevents direct diffusion of impurities between the NMOS and PMOS gate regions, eliminating the harmful interaction while preserving the beneficial work function matching of the dual polysilicon gate structure.
2Area of stationary object
If impurity doped portions are positioned close to minimize N-P space, then device area is reduced, but impurity diffusion into adjacent regions increases
Solution Approach 1:
The gate layer is divided into distinct doped and undoped segments, allowing the impurity-doped portions to be positioned close together for minimal N-P space while the undoped portion acts as a diffusion barrier. This segmentation enables area reduction without sacrificing protection against impurity diffusion.
Solution Approach 2:
The undoped portion serves as an intermediary barrier that allows the first and second impurity-doped portions to be positioned in close proximity while preventing impurity diffusion between them. This intermediary structure enables minimal N-P space without the harmful effect of cross-contamination.
3Reliability
If heat treatment is applied to activate impurities, then electrical properties are improved, but impurity diffusion into adjacent regions occurs
Solution Approach 1:
The gate layer is segmented into doped and undoped regions, allowing heat treatment to activate impurities in the doped portions while the undoped portion prevents diffusion into adjacent regions. This segmentation enables thermal processing to improve electrical properties without sacrificing impurity positioning precision.
Solution Approach 2:
The undoped portion acts as a thermal barrier during heat treatment, allowing impurities to be activated in the doped regions while preventing their diffusion into adjacent regions. This intermediary structure enables improved electrical properties through heat treatment while maintaining precise impurity positioning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents performance deterioration by controlling impurity diffusion, reducing the N-P space, and enhancing the reliability of semiconductor devices, which in turn reduces the circuit area and improves signal transfer rates.
Implementation Method 1
forming a diffusion barrier portion in the gate layer between the first impurity doped portion and the second impurity doped portion
Data Source
AI summary
A semiconductor device includes a substrate including a first active region, a second active region, and an isolation region positioned between the first active region and the second active region; and a gate layer crossing over the first active region, the second active region, and the isolation region, wherein the gate layer includes a first impurity doped portion overlapping with the first active region, a second impurity doped portion overlapping with the second active region, and a diffusion barrier portion positioned between the first impurity doped portion and the second impurity doped portion.