Gate Structure Dipole Interface for Threshold Voltage Modulation
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Solution Overview
Problem
The introduction of high-k materials in transistor gate dielectrics leads to Fermi level pinning, increasing threshold voltage and making it challenging to form metal gate electrodes with appropriate work functions for CMOS devices, while existing solutions face difficulties in maintaining effective work functions during fabrication processes.
Innovation Solution
A semiconductor device with a gate structure that includes a dipole-interface formed by diffusing aluminum in the PMOS region and lanthanum in the NMOS region, allowing independent modulation of threshold voltages for N and P channel transistors, and a reaction preventing layer to stabilize the work function, simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high-k material is introduced as gate dielectric layer, then gate leakage is reduced, but Fermi level pinning effect increases threshold voltage
Solution Approach 1:
A dipole interface layer is introduced as an intermediary between the high-k gate dielectric layer and the metal gate electrode. This dipole interface layer modifies the electrical characteristics at the interface, reducing the Fermi level pinning effect and enabling better control of threshold voltage while maintaining the low gate leakage properties of the high-k material.
Solution Approach 2:
The patent changes the physical and chemical parameters at the gate dielectric-metal electrode interface by forming a dipole interface layer with specific composition and structure. This alters the interface states and energy band alignment, thereby changing the threshold voltage characteristics and reducing Fermi level pinning while preserving the energy loss reduction achieved through high-k material.
2Manufacturing precision
If metal gate electrode with appropriate work function is formed, then threshold voltage is modulated, but effective work function changes during fabrication process
Solution Approach 1:
The dipole interface layer is formed in advance, before the metal gate electrode deposition and subsequent fabrication processes. This preliminary action prepares the interface to resist changes in effective work function that may occur during later high-temperature processing and etching steps, thereby stabilizing the threshold voltage modulation throughout the fabrication process.
Solution Approach 2:
The dipole interface layer serves as a protective intermediary between the metal gate electrode and the high-k dielectric, shielding the metal gate from interactions with the dielectric material and processing environments that would otherwise cause effective work function drift. This mediator maintains the intended electrical characteristics throughout fabrication.
3Ease of manufacture
If polysilicon gate electrode is used, then fabrication is simplified, but Fermi level pinning effect occurs at interface with metal oxide layer
Solution Approach 1:
The gate structure uses a composite arrangement combining high-k dielectric material, dipole interface layer, and metal gate electrode. This composite structure replaces the conventional polysilicon gate while maintaining fabrication compatibility, achieving both improved threshold voltage control and reduced Fermi level pinning through the carefully engineered interface properties of the composite materials stack.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively decreases the threshold voltage of both N and P channel transistors, maintains thermal stability of the gate stack, and simplifies the integration process by preventing changes in the effective work function, enabling high-performance CMOSFETs.
Implementation Method 1
annealing the first stack layer and the second stack layer, thereby forming a first dipole-interface by diffusion of the aluminum in the first gate dielectric layer
Implementation Method 2
forming a second dipole-interface by diffusion of the lanthanum in the second gate dielectric layer
Implementation Method 3
annealing the first stack layer and the second stack layer
Data Source
AI summary
A method for fabricating a semiconductor device includes forming an NMOS region and a PMOS region in a substrate, forming a first stack layer including a first gate dielectric layer and a first work function layer that is disposed over the first gate dielectric layer and contains aluminum, over the PMOS region of the substrate, forming a second stack layer including a second gate dielectric layer, a threshold voltage modulation layer that is disposed over the second gate dielectric layer and contains lanthanum, and a second work function layer that is disposed over the threshold voltage modulation layer, over the NMOS region of the substrate, and annealing the first stack layer and the second stack layer, thereby forming a first dipole-interface by diffusion of the aluminum in the first gate dielectric layer and a second dipole-interface by diffusion of the lanthanum in the second gate dielectric layer, respectively.