Gate Interfacial Dipole Layers for Threshold Voltage Tuning
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Solution Overview
Problem
Conventional methods for tuning threshold voltage in semiconductor devices face challenges as device scaling down progresses, making it difficult to increase the thickness of work function metals, which can lead to manufacturing difficulties and limited flexibility in threshold voltage tuning.
Innovation Solution
The formation of a dipole layer directly on an interfacial layer in a gate structure, combined with multiple interfacial-layer-patterning processes, allows for different threshold voltages to be achieved for various devices, improving flexibility and reducing gate resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the thickness of work function metals is increased to tune threshold voltage, then threshold voltage tuning capability is improved, but manufacturing difficulty increases and device scaling becomes unfeasible
Solution Approach 1:
The patent changes the approach from adjusting metal thickness to adjusting dipole layer composition and structure. By modifying the dipole layer's material composition, thickness, and positioning relative to the channel, the invention achieves threshold voltage tuning without increasing work function metal thickness, thereby maintaining manufacturability in scaled devices
Solution Approach 2:
The patent introduces a dipole layer as an intermediary between the gate electrode and the channel. This dipole layer mediates the electric field interaction, allowing threshold voltage control through its dipole moment rather than through direct control of work function metal thickness, thus avoiding the manufacturing difficulties associated with thick metal layers
2Adaptability or versatility
If the thickness of work function metals is increased to tune threshold voltage, then threshold voltage tuning capability is improved, but device geometry scaling becomes unfeasible
Solution Approach 1:
The invention transitions from a thickness-based tuning parameter to a composition-based tuning parameter. By controlling the dipole layer's material composition and structural parameters rather than metal thickness, the solution enables effective threshold voltage tuning in highly scaled devices where thickness control becomes impractical
Solution Approach 2:
The patent moves the tuning mechanism from the vertical dimension (metal thickness) to the compositional and positional dimensions of the dipole layer. This dimensional shift allows tuning flexibility without being constrained by the minimum thickness requirements imposed by device scaling
3Ease of manufacture
If conventional gate structures are used, then manufacturing process is simple, but threshold voltage tuning flexibility is limited
Solution Approach 1:
The dipole layer serves multiple functions: it provides threshold voltage tuning, controls interface properties, and enables device type differentiation (PFET vs NFET) through selective application. This multi-functionality achieves tuning flexibility without significantly complicating the manufacturing process
Solution Approach 2:
The patent applies different dipole layer configurations to different device regions or types. By locally tailoring the dipole layer properties (presence, composition, thickness) to specific device requirements, the invention achieves high tuning flexibility while maintaining a generally simple and scalable manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more flexible tuning of threshold voltage and reduces gate resistance compared to conventional devices, without the need to adjust the thickness of work function metal layers.
Implementation Method 1
forming a dipole layer directly on an interfacial layer in a gate structure
Data Source
AI summary
A semiconductor device includes a first gate structure that includes a first interfacial layer, a first gate dielectric layer disposed over the first interfacial layer, and a first gate electrode disposed over the first gate dielectric layer. The semiconductor device also includes a second gate structure that includes a second interfacial layer, a second gate dielectric layer disposed over the second interfacial layer, and a second gate electrode disposed over the second gate dielectric layer. The first interfacial layer contains a different amount of a dipole material than the second interfacial layer.