Gate Structure Dipole Layer Tuning Threshold Voltage
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Solution Overview
Problem
Conventional methods for tuning threshold voltage in semiconductor devices face challenges as they become increasingly difficult to implement due to the limitations of scaling down processes, particularly in adjusting the thickness of work function metals, which can lead to manufacturing difficulties and reduced flexibility in achieving desired threshold voltages.
Innovation Solution
The formation of a dipole layer directly on an interfacial layer in a gate structure, combined with multiple interfacial-layer-patterning processes, allows for the tuning of threshold voltages by varying the amount of dipole material penetration, reducing gate resistance and enabling different threshold voltages for various devices without the need to adjust work function metal thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the thicknesses of work function metals are increased to tune threshold voltage, then threshold voltage tuning is achieved, but manufacturing difficulty increases and flexibility is reduced due to scaling down limitations
Solution Approach 1:
The patent changes the parameter being adjusted from work function metal thickness to dipole layer thickness. By forming dipole layers of varying thicknesses (e.g., 1-5 nm) through controlled deposition processes, the invention achieves threshold voltage tuning without the manufacturing complexities associated with adjusting metal thickness at scaled dimensions. This parameter substitution resolves the contradiction by maintaining tuning precision while improving ease of manufacture.
Solution Approach 2:
The dipole layer serves as an intermediary between the gate dielectric and the channel, mediating the threshold voltage adjustment function. Instead of directly adjusting work function metal thickness, the invention introduces dipole layers that create electric dipole moments at the interface, thereby tuning threshold voltage through a intermediate mechanism that is more compatible with scaled manufacturing processes.
2Adaptability or versatility
If the thicknesses of work function metals are adjusted to achieve different threshold voltages, then threshold voltage tuning is possible, but device complexity increases due to multiple patterning requirements
Solution Approach 1:
The invention segments the threshold voltage tuning function into separate dipole layer formations for different device regions. By applying dipole layers selectively to first, second, and third gate structures with different thicknesses or material compositions, the patent achieves multiple threshold voltage levels without requiring complex multi-step patterning of work function metals. This segmentation approach maintains adaptability while reducing processing complexity.
Solution Approach 2:
The patent applies local quality by creating spatial variations in dipole layer properties (thickness, material composition) at specific gate structure locations. Different gate structures receive dipole layers with tailored characteristics to achieve desired threshold voltages locally, eliminating the need for global work function metal thickness adjustments and reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the flexibility in tuning threshold voltages and reduces gate resistance by allowing different amounts of dipole material to penetrate into the interfacial layer, optimizing threshold voltage settings for different devices without the limitations of conventional methods.
Implementation Method 1
perform a dipole drive-in process to drive in a material of the dipole layer into the first interfacial layer and the second interfacial layer
Data Source
AI summary
A semiconductor device includes a first gate structure that includes a first interfacial layer, a first gate dielectric layer disposed over the first interfacial layer, and a first gate electrode disposed over the first gate dielectric layer. The semiconductor device also includes a second gate structure that includes a second interfacial layer, a second gate dielectric layer disposed over the second interfacial layer, and a second gate electrode disposed over the second gate dielectric layer. The first interfacial layer contains a different amount of a dipole material than the second interfacial layer.