Gate Dielectric Dipole Region for FinFET Vt Tuning
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Solution Overview
Problem
The challenge in electronic device manufacturing lies in maintaining switching speeds and controlling device structure dimensions as device geometries shrink, particularly for FinFET devices, where the migration of transistor technology requires conformal work function layers for multiple threshold voltages, and the tuning range is limited by film thickness variation.
Innovation Solution
A method involving the deposition of an interfacial layer, a high-κ dielectric layer, and a dipole layer comprising strontium (Sr), yttrium (Y), ytterbium (Yb), antimony (Sb), or tellurium (Te) on a substrate, followed by annealing at a temperature of less than or equal to 1050°C to drive atoms into the high-κ dielectric layer, enhancing the threshold voltage (Vt) without increasing equivalent oxide thickness (EOT).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are shrunk to increase functional density, then more devices can be integrated per chip area, but switching speeds deteriorate and device structure control becomes difficult
Solution Approach 1:
The patent changes the physical and chemical parameters of the gate dielectric layer by forming a dipole region with specific metal nitrides (Sr, Y, Yb, Sb, or Te) at the interface. This modifies the electrical properties (threshold voltage) without changing the geometric dimensions, allowing continued scaling while maintaining device performance
Solution Approach 2:
The dipole region is localized at the specific interface between the gate dielectric and channel, creating a concentrated effect zone. This local modification of the interface properties enables precise threshold voltage control without affecting the overall device geometry or requiring global dimensional changes
2Length of stationary object
If film thickness is reduced to enable further scaling, then device size decreases, but Vt tuning range becomes limited
Solution Approach 1:
Instead of relying solely on thickness variation for Vt tuning, the patent introduces a chemical parameter change by forming a dipole region with metal nitrides. This creates an additional degree of freedom for Vt control, allowing extensive tuning range even with reduced film thickness
Solution Approach 2:
The gate dielectric structure becomes a composite system combining the dielectric material with a dipole region formed by metal nitrides. This composite structure provides both the insulating properties of the dielectric and the electrical property modulation capability of the dipole layer, enabling independent optimization of thickness and Vt tuning
3Adaptability or versatility
If conventional dipole formation methods are used, then Vt can be tuned, but equivalent oxide thickness (EOT) increases
Solution Approach 1:
The dipole region is confined to a very thin interface zone within the gate dielectric, creating a highly localized effect. This concentrated dipole formation achieves strong Vt modulation without requiring thick additional layers, thus minimizing EOT increase
Solution Approach 2:
The use of metal nitride dipoles within the high-κ dielectric creates a composite structure that provides enhanced dipole moment per unit thickness. This allows achieving the required Vt tuning with minimal additional thickness penalty compared to conventional dipole materials
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves Vt significantly while minimizing EOT increase, providing at least 50 mV Vt shift with minimal EOT penalty, effectively addressing the limitations of existing technologies in FinFET device manufacturing.
Implementation Method 1
annealing the substrate at a temperature of less than or equal to 1050° C. to drive atoms from the dipole layer into the high-κ dielectric layer
Implementation Method 2
depositing an interfacial layer on a top surface of a channel located between a source and a drain on a substrate; depositing a high-κ dielectric layer on the interfacial layer; depositing a dipole layer on the high-κ dielectric layer
Data Source
AI summary
Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise a dipole region and meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of the channel, a high-κ dielectric layer on the interfacial layer, a dipole layer on the high-κ dielectric layer, and optionally, a capping layer on the dipole layer. In some embodiments, the methods comprise annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-κ dielectric layer.