Gate-Drain Layout With Extended LDD to Suppress GIDL
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Solution Overview
Problem
As integrated circuits scale down, the reduced distance between the gate structure and drain region in transistors leads to significant gate-induced drain leakage (GIDL) current, which is not adequately addressed by existing technologies.
Innovation Solution
Incorporating an elongated lightly doped region between the gate structure and the drain region, which increases the distance and reduces GIDL current, while maintaining transistor size and functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between gate structure and drain region is reduced to increase functional density, then production efficiency and cost are improved, but gate-induced drain leakage current increases
Solution Approach 1:
An intermediate region is introduced between the gate structure and drain region to mediate the interaction. This intermediate region acts as a buffer zone that prevents direct harmful interaction between the gate and drain, thereby reducing GIDL current while maintaining the scaled-down geometry for high productivity
Solution Approach 2:
The patent applies different doping concentrations locally within the transistor structure. Specifically, the region adjacent to the gate structure has a lower doping concentration compared to the bulk drain region, creating a local quality variation that reduces electric field intensity and suppresses GIDL current in the critical area near the gate
2Object-generated harmful factors
If the distance between gate structure and drain region is increased to reduce GIDL current, then leakage current is suppressed, but functional density and transistor size increase
Solution Approach 1:
Instead of uniformly increasing the distance between gate and drain, the patent applies a localized modification where only the region immediately adjacent to the gate structure has reduced doping concentration. This local quality change suppresses GIDL current without requiring a global increase in transistor dimensions, thereby maintaining high functional density
Solution Approach 2:
The patent changes the doping concentration parameter locally in the region adjacent to the gate structure. By reducing the doping concentration in this specific region while maintaining higher doping in other areas, the electric field distribution is modified to suppress GIDL current without increasing the overall transistor size or reducing functional density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses GIDL current without significantly increasing transistor size, enabling efficient operation in density-oriented circuits such as micro organic light-emitting diode (μOLED) pixel driver circuits.
Implementation Method 1
the reduced distance between the gate structure and drain region in transistors leads to significant gate-induced drain leakage (GIDL) current
Data Source
AI summary
A device includes a first gate structure, a first gate spacer and a second gate spacer, a first lightly doped drain region, a first drain region, a first protection layer, and a first drain silicide region. The first gate structure is over a substrate. The first gate spacer and a second gate spacer are on opposite sides of the first gate structure, respectively. The first lightly doped drain region laterally extends from directly below the first gate spacer to past an outermost sidewall of the first gate spacer. The first drain region laterally extends from the first lightly doped drain region in a direction away from the first gate structure. The first protection layer is over the first lightly doped drain region. The first drain silicide region is over the first drain region and contacts an end surface of the first protection layer.