Gate Drive Circuit Capacitance Compensation for 8K Display Uniformity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
1G1D 8K display products face issues with horizontal lines and uneven brightness due to large capacitance differences between clock signal lines in the gate drive circuit, leading to display quality problems.
Innovation Solution
A gate drive circuit with N clock signal lines and gate drive units, each equipped with capacitance compensation units to balance the area and capacitance of clock signal lines, ensuring equal capacitance across all lines, thereby balancing the falling time of scan signals and preventing horizontal dense lines and uneven brightness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signal lines are used in the gate drive circuit without capacitance compensation, then the circuit structure is simple, but large capacitance differences between clock signal lines cause scan signal waveform differences leading to horizontal lines with equal spacing
Solution Approach 1:
The patent applies local quality by introducing capacitance compensation units at specific locations (blank areas) of gate drive units that are connected to clock signal lines. These compensation units are selectively placed only where needed - specifically at gate drive units connected to clock signal lines with larger capacitance differences - rather than uniformly across all gate drive units. This localized approach balances the capacitance values of different clock signal lines to eliminate scan signal waveform differences and horizontal line defects, while minimizing the overall increase in device complexity by avoiding unnecessary compensation units throughout the entire circuit.
2Reliability
If capacitance compensation units are added to all gate drive units, then capacitance balance is improved, but the device area and complexity increase
Solution Approach 1:
The patent implements local quality by placing capacitance compensation units only in blank areas of specific gate drive units that are connected to clock signal lines requiring compensation. The compensation units are positioned in unused spaces within the gate drive unit structure, utilizing otherwise wasted area. This approach achieves capacitance balance across clock signal lines while minimizing additional device area consumption, as the compensation units are integrated into existing blank regions rather than requiring separate dedicated spaces.
Solution Approach 2:
The patent applies the nesting principle by embedding capacitance compensation units within the blank areas of gate drive units. The compensation units are nested inside the existing gate drive unit structure, specifically utilizing unused spaces within the transistor and capacitor arrangements. This nested placement allows the compensation functionality to be integrated into the existing device footprint without requiring significant additional area, effectively hiding the compensation structures within the available spaces of the gate drive units.
3Ease of manufacture
If clock signal lines have different capacitance values, then the circuit layout is flexible, but scan signals loaded on scan lines become sensitive to capacitance differences causing display issues
Solution Approach 1:
The patent applies parameter changes by modifying the capacitance values of clock signal lines through the addition of capacitance compensation units. These compensation units adjust the effective capacitance parameters of individual clock signal lines to achieve uniform capacitance values across all lines. By changing the capacitance parameter from non-uniform to uniform values, the patent eliminates the sensitivity of scan signals to capacitance differences, preventing waveform variations and horizontal line defects while maintaining layout flexibility through selective placement in blank areas.
Data Source
AI summary
A gate drive circuit and a display panel are provided. The gate drive circuit includes N clock signal lines and a plurality of gate drive units. Each of the gate drive units is connected to at least one of the clock signal lines. Each of the clock signal lines is provided with a capacitance compensation unit, a sum of an area of any one of the clock signal lines and an area of the capacitance compensation unit provided on the same clock signal line is equal to a predetermined area, and N is an integer greater than or equal to 2.