Gate Drive Circuit Vertical Blanking Signal Control
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Solution Overview
Problem
In liquid crystal display (LCD) apparatuses, integrated gate drive circuits on display substrates experience abnormal gate signals during high-temperature operation and vertical blanking intervals, leading to display defects due to parasitic capacitors causing intermittent gate on signals during gate off intervals.
Innovation Solution
A method and circuit design that applies a gate off voltage to gate lines during vertical blanking intervals by blocking the output of shift registers using an output control part, preventing the output signal from floating and thus avoiding the generation of abnormal gate signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the gate drive circuit is integrated on the display substrate, then the size of the LCD apparatus is decreased and productivity is enhanced, but abnormal gate signals are generated during high-temperature operation and vertical blanking intervals
Solution Approach 1:
The patent applies a gate off voltage to the gate lines during the vertical blanking interval before the next gate on signal is generated. This preliminary action prevents the parasitic capacitor from causing abnormal gate signals by ensuring the gate line is properly discharged and stabilized before the next operation cycle begins.
Solution Approach 2:
The patent introduces an output control part that acts as an intermediary between the shift register and the gate line. This intermediary component controls the timing of signal output, blocking the output during the vertical blanking interval and ensuring proper voltage application to prevent display defects.
2Device complexity
If the output signal of the gate drive circuit is allowed to float during vertical blanking interval, then the circuit operation is simplified, but the off voltage of the gate electrode increases due to parasitic capacitor
Solution Approach 1:
The output control part is configured to block the output signal during the vertical blanking interval, ensuring that the gate line voltage is properly controlled before the next gate on signal. This preliminary control action prevents voltage drift caused by parasitic capacitors without requiring complex additional circuitry.
Solution Approach 2:
The patent applies a gate off voltage during the vertical blanking interval to counteract the effect of parasitic capacitors before they can cause abnormal gate signals. This preliminary anti-action prevents the harmful effect of voltage drift and ensures stable gate electrode voltage.
3Ease of operation
If the gate off voltage is not applied during vertical blanking interval, then the circuit operation is simpler, but intermittent gate on signals are generated during gate off signal interval
Solution Approach 1:
The output control part blocks the output during the vertical blanking interval and applies gate off voltage to the gate lines. This preliminary action ensures that the gate line is properly prepared before the next gate on signal, preventing intermittent gate on signals and display defects without significantly complicating the circuit operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces display defects by maintaining a gate off voltage during vertical blanking intervals, preventing signal float and ensuring stable gate operation, thereby enhancing the reliability of the LCD apparatus.
Implementation Method 1
an off voltage of a gate electrode may increase due to a parasitic capacitor (Cgd) between the gate line and the data line
Data Source
AI summary
There is provided a method of driving a gate line, a gate drive circuit for performing the method, and a display apparatus having the gate drive circuit. In the method, a plurality of gate signals, generated from a plurality of shift registers connected to a plurality of gate lines, is applied to the gate lines. An output of the gate signals is blocked during a vertical blanking interval, and then a gate off voltage is applied to the gate lines. Therefore, an output signal of the gate drive circuit may maintain a gate off voltage during a vertical blanking interval in which a clock signal is not applied to a gate drive circuit.