Gate Drive Circuit Charge Control for Power Transistors
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Solution Overview
Problem
Existing gate drive circuits for power transistors, such as IGBTs, face challenges in accurately controlling the charge across boost capacitors, leading to inefficient switching speeds and potential damage due to unregulated gate voltages, which are either too low and cause excessive losses or too high and result in transistor destruction.
Innovation Solution
A gate drive circuit that includes a first capacitor pre-charged to a second predetermined voltage, a switch to control the capacitor's connection to a first predetermined voltage, and a measurement circuit to monitor and regulate the differential voltage across the capacitor, ensuring accurate transfer of charge to the gate capacitor, thereby controlling the gate voltage accurately and preventing damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a boost capacitor is added in series with the gate contact resistance to speed up turning on, then switching speed is improved, but charge control accuracy deteriorates
Solution Approach 1:
The patent implements a feedback control mechanism where a measurement circuit continuously monitors the voltage across the boost capacitor and compares it with a reference voltage. When the measured voltage reaches the reference level, a control signal is generated to disconnect the charging path, preventing overcharging. This closed-loop feedback system enables precise control of the charge stored in the boost capacitor, resolving the contradiction between achieving fast switching and maintaining accurate charge control.
2Reliability
If the gate voltage is forced to +15 V to guarantee proper gate voltage, then full conductivity is achieved, but switching speed becomes too slow
Solution Approach 1:
The patent applies preliminary action by pre-charging the boost capacitor to a specific voltage level (e.g., +15 V or higher) before the actual switching operation. This pre-prepared charge is then rapidly transferred to the gate terminal when switching is required, enabling fast switching while ensuring the gate voltage reaches the necessary +15 V for full conductivity. The RC time constant of the gate circuit determines the final settling time, but the preliminary charge preparation eliminates the need for slow charging during the critical switching moment.
3Loss of energy
If the gate voltage is too low, then switching losses increase, but if the gate voltage is too high, then transistor destruction occurs
Solution Approach 1:
The feedback control mechanism monitors the boost capacitor voltage and disconnects the charging path when the voltage reaches a predetermined reference level. This prevents the gate voltage from exceeding the maximum safe value (typically +15 V for IGBTs) while ensuring it reaches sufficient levels for low-loss conduction. The reference voltage is carefully selected to correspond to the optimal gate voltage that achieves full conductivity without risking transistor damage, thus resolving the contradiction between minimizing switching losses and preventing transistor destruction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables precise control of the gate voltage, ensuring fast switching speeds with minimal losses and preventing damage to the IGBT, while maintaining the required +15 V for full conductivity, thus improving the overall performance and reliability of the power transistor.
Implementation Method 1
a first capacitor (C1) having a first terminal (T11) electrically coupled to the gate terminal (G) of the power transistor (12a)
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
A gate drive circuit (10a) to drive a gate terminal (G) of a power transistor (12a). The gate drive circuit (10a) includes a first capacitor (C1), a first switch (SW1), a measurement circuit (5) and a reference source (6) to generate a reference voltage (Vref). The first capacitor (C1) has a first terminal (T11) electrically coupled to the gate terminal (G) of the power transistor (12a). The first switch (SW1) is arranged between a second terminal (T21) of the first capacitor (C1) and a first predetermined voltage (Vp1). The measurement circuit (5) is used to measure a differential voltage across the first capacitor (C1). The gate drive circuit (10a) is configured to pre-charge the first capacitor (C1) to obtain a second predetermined voltage (Vp2) across the first capacitor (C1). The gate drive circuit (10a) is further configured to arrange the first switch (SW1) in an on state to turn on the power transistor (12a) and to electrically couple the first predetermined voltage (Vp1) to the second terminal (T21) of the first capacitor (C1). The first capacitor (C1) is initially pre-charged at the second predetermined voltage (Vp2). The measurement circuit (5) is configured to arrange the first switch (SW1) in an off state when the differential voltage across the first capacitor (C1) has changed with respect to the second predetermined voltage (Vp2) by the reference voltage (Vref). By using the measurement circuit (5) to measure the differential voltage across the first capacitor (C1) and to turn off the first switch (SW1) when the differential voltage across the first capacitor (C1) has changed with respect to the second predetermined voltage (Vp2) by the reference voltage (Vref), an accurate control of the charge change in the first capacitor (C1) is provided. The charge change proportional to the reference voltage (Vref) is a measure of an amount of charge that is transferred to the gate terminal (G) of the power device (12a) to turn on the power device (12a).