Gate Drive Circuit RC Delay Reduction via Boost Capacitor Decoupling

The patent segments the gate drive circuit into multiple stages (first gate drive unit, second gate drive unit, etc.) with each stage having independent boost capacitors and control circuits. This segmentation allows the boost capacitor to be isolated from the gate line, eliminating the parasitic capacitance effect while maintaining the potential boosting function through staged operation.

The patent introduces an intermediate node (node Q) and a transfer circuit between the boost capacitor and the gate line. The boost capacitor connects to node Q, and a transfer circuit (including transistors and switches) mediates the charge transfer from node Q to the gate line when needed. This intermediary structure prevents the boost capacitor from being a direct parasitic capacitor on the gate line while still enabling potential boosting when required.

The gate drive circuit is divided into multiple stages, with each stage responsible for driving a portion of the gate lines. Each stage has its own boost capacitor and control circuitry, allowing independent optimization. This segmentation reduces the effective load capacitance seen by each boost capacitor, thereby reducing RC delay while supporting higher resolution panels.

The patent implements preliminary charging of node Q through the boost capacitor before the actual gate drive signal is transmitted. The transfer circuit is configured to transfer charge from node Q to the gate line at the appropriate timing. This preliminary action ensures that the gate line is pre-charged, reducing the RC delay effect during the actual signal transmission, which is particularly beneficial for high-resolution panels with larger load capacitance.