Gate Drive Circuit for LCD Charging Uniformity
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Solution Overview
Problem
Large-size and high-resolution LCD panels with narrow frame designs face issues of uneven charging due to non-uniform gate line resistance, leading to unsaturated charging voltage and inconsistent brightness across sub-pixels, resulting in low grayscale and dark lines.
Innovation Solution
A gate drive circuit with N array substrate row drive circuits arranged in cascade and N auxiliary circuits, where each auxiliary circuit controls sub-pixels to charge when both the timing and pull-up control signals are high, ensuring simultaneous charging across all sub-pixels and compensating for uneven wiring effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If narrow frame design is adopted for large-size and high-resolution LCD panels, then the display area is increased and frame ratio is improved, but uneven charging occurs due to non-uniform gate line resistance
Solution Approach 1:
The gate drive circuit is divided into multiple stages (first stage, second stage, third stage) with each stage driving a specific region of the gate lines. This segmentation allows independent optimization of drive signals for different regions, compensating for the non-uniform resistance characteristics in narrow frame designs.
Solution Approach 2:
Different drive strategies are applied to different regions: the first stage drives gate lines in a first region, the second stage drives gate lines in a second region, and the third stage drives gate lines in a third region. Each stage uses locally adapted drive signals to achieve uniform charging across the entire display area despite varying resistance.
2Device complexity
If gate drive circuit is arranged at the side frame, then narrow frame design is enabled, but equal resistance setting wiring cannot be performed between each gate line and the gate driver
Solution Approach 1:
The gate drive circuit is extended into the display area along the gate line direction, transitioning from a purely side-frame arrangement to a multi-dimensional layout. This allows the circuit to physically接近 different gate line regions and implement region-specific drive strategies.
Solution Approach 2:
The gate drive circuit employs dynamic control with multiple stages that can independently adjust their drive signals. The first, second, and third stages dynamically switch between different drive modes to compensate for position-dependent resistance variations in the narrow frame design.
3Productivity
If cascade arrangement of array substrate row drive circuits is used, then gate drive signals can be sequentially transmitted, but charging saturation cannot be achieved due to signal attenuation
Solution Approach 1:
The first stage gate drive circuit performs preliminary charging of the gate lines before the second and third stages take over. This staged, sequential approach ensures that each stage builds upon the charging work of the previous stage, achieving full saturation despite signal attenuation through the cascade arrangement.
Solution Approach 2:
The multiple stages operate in continuous sequence, with each stage maintaining and enhancing the charging effect of the previous stage. This continuous action through three stages ensures that charging saturation is achieved and maintained across all gate lines despite the cascade configuration.
Data Source
AI summary
A gate drive circuit includes: N array substrate row drive circuits arranged in cascade, an Nth array substrate row drive circuit is configured for outputting an Nth gate drive signal in response to a signal input terminal receiving a gate drive signal output by an N−1th array substrate row drive circuit to control Nth sub-pixels to charge; N auxiliary circuits, a timing signal input terminal is connected to an Nth timing control signal, a controlled terminal is connected to a pull-up control signal terminal of the N−1th array substrate row drive circuit, and an output terminal is connected to a gate drive signal output terminal; and the Nth auxiliary circuit is configured for controlling the Nth sub-pixels to charge in a determination that the Nth timing control signal connected to the timing signal input terminal and an N−1th pull-up control signal connected to the controlled terminal are both high level.