Gate Drive Circuit Shift Register Ripple Reduction
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Solution Overview
Problem
In liquid crystal display (LCD) devices, the parasitic capacitance of the gate drive circuit's pull-up element increases, leading to signal instability due to ripple generation during the gate off signal interval, making it difficult to maintain a stable pull-up function.
Innovation Solution
A gate drive circuit with a shift register structure, featuring transistors with varying channel lengths and widths, including a discharging part, first and second holding parts, and a buffering part, to manage clock signals and voltage levels, reducing ripple and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the parasitic capacitance of the pull-up element is increased, then the pull-up strength is enhanced, but ripple is generated during the gate off signal interval causing signal instability
Solution Approach 1:
The holding function is segmented into two independent n-type transistors that operate during different intervals. The first holding transistor operates during the gate on signal interval to maintain high level, while the second holding transistor operates during the gate off signal interval to maintain low level. This segmentation prevents the ripple generation issue while maintaining adequate pull-up capability.
Solution Approach 2:
The circuit employs periodic action by alternating the operation of the first and second holding transistors based on the clock signal intervals. During the gate on interval, the first holding transistor is active; during the gate off interval, the second holding transistor is active. This periodic switching eliminates ripple while maintaining signal stability throughout the complete cycle.
Data Source
AI summary
A gate drive circuit includes a shift register having stages connected to each other in series. An (m)-th stage (‘m’ is a natural number) includes an output part, a discharging part, a first holding part and a second holding part. The output part outputs the first clock signal as a gate signal in response to a first clock signal provided from an external device and discharges the gate signal in response to a second input signal. The output part includes a first transistor having a first channel length. The discharging part discharges a signal of the first node to the second voltage level. The first holding part maintains a signal of the first node at a level of the gate signal, and is discharged to the second voltage level. The first holding part includes a second transistor having a second channel length that is longer than the first channel length. The second holding part maintains a signal of the first node at a level of the second voltage level.