Gate Drive Circuit Stabilizing Output Voltage in Display Devices

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Solution Overview

Problem

In display devices, the reduced number of thin-film transistors (TFTs) in mobile devices leads to unstable output voltages due to floating periods, causing voltage fluctuations and degrading picture quality and device lifetime, especially under DC gate bias stress and varying temperatures.

Innovation Solution

A gate drive circuit with a pull-up transistor and a switching circuit, including an inverter circuit, is used to stabilize output voltages by controlling the Q node and QB node voltages, and a pull-down transistor with a reverse bias is applied during power-off to recover from threshold voltage shifts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the number of TFTs is reduced to reduce the bezel of the display panel, then the area of the display panel is improved, but the stability of output voltage deteriorates due to floating periods

Engineering Contradiction:
Improvebezel areaVSAvoidoutput voltage stability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent applies preliminary action by proactively managing the floating period issue through a compensation circuit that pre-charges or pre-discharges the Q node and output node before the floating period occurs. This prevents voltage fluctuations from happening in the first place, rather than reacting to them after they occur. The circuit uses clock signals to control switching elements that prepare the nodes for the upcoming floating period, ensuring stable voltages are maintained throughout the cycle.

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If DC gate bias stress is applied to turn on TFTs, then the switching function is improved, but the threshold voltage shifts and device lifetime is reduced

Engineering Contradiction:
ImproveTFT switching functionVSAvoiddevice lifetime
Core Design Contradiction:
Ease of operationVSDuration of action of stationary object

Solution Approach 1:

The patent implements periodic action by alternating between positive DC gate bias stress and reverse bias stress in a cyclic manner. During normal operation, positive bias turns on the TFTs for switching. Periodically, reverse bias is applied to compensate for threshold voltage shifts. This periodic alternation between opposing actions (positive bias for switching, negative bias for compensation) maintains TFT performance over time while extending device lifetime.

Inventive Principle:
Principle #19Periodic action

3Reliability

If a compensation circuit is added to stabilize output voltages, then the reliability is improved, but the device complexity increases

Engineering Contradiction:
Improveoutput voltage stabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing a compensation circuit that performs multiple functions simultaneously. The same switching elements and nodes used for normal gate drive operations are also utilized for compensation purposes. The circuit uses existing clock signals for both timing control and compensation control. This multi-functionality allows voltage stabilization without adding separate dedicated compensation components, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10019929B2Gate drive circuit and display device using the same
Publication Date: 2018.07.10 LG DISPLAY CO LTD
  • US10019929B2 patent drawing
  • US10019929B2 patent drawing
  • US10019929B2 patent drawing

AI summary

A display device having a plurality of gate lines and a gate drive circuit is disclosed. The gate drive circuit includes a pull-up transistor configured to receive a first clock signal and to charge an output node to a voltage of the first clock signal based on a voltage of a Q node. The output node is connected to a corresponding one of the gate lines. The gate drive circuit also includes a switching circuit configured to charge the Q node based on a second clock signal. The switching circuit has an inverter circuit configured to control the voltage of the Q node based on the second clock signal.