Gate Drive Clock Routing to Equalize Scan Pulse Timing
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Solution Overview
Problem
The existing gate drive circuits for display devices experience load deviations between connecting units due to varying distances between clock transmission lines and the shift register, leading to increased ascending and descending time deviations in scan pulses, which degrade image quality.
Innovation Solution
A gate drive circuit design that includes at least two clock transmission lines with phase differences, a shift register, and zigzagged connecting units to minimize load differences between connecting units, ensuring consistent clock pulse states and reduced signal interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If straight connecting units are used to connect clock transmission lines to the shift register, then the circuit structure is simple, but load differences occur due to varying distances causing ascending and descending time deviations in scan pulses
Solution Approach 1:
The connecting units are designed with different structures at different locations. Specifically, connecting units closer to the shift register have zigzagged portions while those farther away have straight portions, creating local variations in electrical length to compensate for distance differences and achieve uniform load conditions across all connecting units.
Solution Approach 2:
The electrical parameters of the connecting units are adjusted by changing their physical geometry. By introducing zigzagged portions with specific lengths and patterns, the electrical length of each connecting unit is modified to compensate for variations in distance from the shift register, thereby equalizing the load conditions.
2Area of stationary object
If connecting units of different lengths are used to accommodate varying distances, then the physical layout is optimized, but load differences cause inter-clock pulse ascending and descending time deviations
Solution Approach 1:
The zigzagged connecting units are designed to create equal electrical lengths despite varying physical distances. By adjusting the zigzag patterns, all connecting units present the same electrical characteristics to the shift register, achieving equipotential conditions that eliminate timing deviations in clock pulses.
3Reliability
If the distance between shift register and clock transmission lines is minimized, then signal strength is improved, but routing flexibility and layout options are reduced
Solution Approach 1:
Instead of only adjusting the physical distance between the shift register and clock transmission lines, the invention introduces zigzagged portions in the connecting units. This adds a dimensional aspect to the connection design, allowing flexible routing while maintaining consistent electrical characteristics through the zigzag patterns.
Data Source
AI summary
A gate drive circuit for a display device is disclosed, by which output states of scan pulses are identically maintained in a manner of minimizing load deviation between connecting units. The present disclosure includes at least two clock transmission lines transmitting at least two clock pulses having a phase difference in-between, a shift register outputting scan pulses sequentially based on the clock pulses transmitted from the clock transmission lines, and a plurality of connecting units connecting the clock transmission lines to the shift register, respectively, wherein at least one of the connecting units is zigzagged in part, the at least one connecting unit comprising: a pad connected to the corresponding clock transmission line via a pad connecting unit; a zigzagged line connected to one side of the pad; and a connecting line that has one side connected to the zigzagged line and the other side connected to the shift register.