Gate Drive Timing Control for Parallel Power Device Current Balancing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current gate drive systems for power devices face challenges in reducing current unevenness among parallel-connected power devices, leading to increased costs and shortened device life due to heat generation and residual defect density issues in high-withstand-voltage applications.
Innovation Solution
A gate drive circuit and system that includes an objective waveform generation unit, drive waveform generation unit, drive control unit, state detection unit, and update unit to synchronize the on/off timing of power devices, reducing current unevenness by adjusting the drive timing based on detected states and predicted waveforms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dead time is secured to avoid concurrent turning on of series-connected power devices, then switching safety is improved, but PWM period becomes too long for high-frequency driving
Solution Approach 1:
The patent applies local quality by individually adjusting the drive timing for each power device based on its specific characteristics. The drive waveform generation unit sets different on-timing and off-timing for each device, allowing localized optimization of switching timing rather than applying a uniform dead time to all devices. This enables high-frequency PWM operation while maintaining switching safety for each device.
2Object-affected harmful factors
If all wiring lines and lead frames are set to equal length and equal parasitic LCR to cancel parasitic effects, then electromagnetic interference is reduced, but current unevenness among parallel power devices persists due to operation timing differences
Solution Approach 1:
The patent applies dynamics by making the drive timing adjustable and adaptable rather than fixed. The drive waveform generation unit dynamically sets on-timing and off-timing for each power device based on detected operation states and timing deviations. This dynamic adjustment compensates for current unevenness caused by timing differences, achieving uniform current distribution among parallel devices even with equal wiring configurations.
3Ease of manufacture
If a relatively small maximum allowable current is decided on to keep power device cost low, then device cost is reduced, but device life is shortened due to residual defect density in SiC substrate when large current flows
Solution Approach 1:
The patent applies feedback by detecting the actual operation timing and current state of each power device, comparing it with the predicted waveform, and using this information to update and refine the drive timing for subsequent cycles. This feedback mechanism ensures that current distribution remains uniform and prevents any single device from carrying excessive current, thereby extending device life while maintaining cost-effectiveness.
4Manufacturing precision
If drive timing is adjusted to synchronize on/off timing of parallel power devices, then current unevenness is reduced, but device complexity increases due to additional control units and timing adjustment mechanisms
Solution Approach 1:
The patent applies merging by integrating the timing adjustment and synchronization functions into a single drive waveform generation unit that works in conjunction with the existing state detection and drive control units. Rather than adding separate complex control systems, the invention combines timing adjustment capabilities within the existing control architecture, reducing overall system complexity while achieving current uniformity.
Data Source
AI summary
Provided is a gate drive circuit and a gate drive system, with which current unevenness among power devices connected in parallel can be reduced more. A gate drive circuit includes: an objective waveform generation unit configured to generate an objective waveform; a drive waveform generation unit configured to generate a drive waveform from the objective waveform, by referring to on-timing set information and off-timing set information; a drive control unit configured to drive the power device to turn the power device on/off, based on the drive waveform; a state detection unit configured to detect the state of the power device; a predicted waveform generation unit configured to generate a predicted waveform of a voltage; and an update unit configured to update the on-timing set information and the off-timing set information, based on the result of the state detection and the result of comparison to the predicted waveform.