Gate Drive Edge-Rate Control for Fast Switching With Lower EMI
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Solution Overview
Problem
Existing edge rate control circuits in amplifiers face challenges in reducing output transition time while maintaining performance, as quick turn-on and turn-off of output field effect transistors lead to electromagnetic interference (EMI) and performance degradation due to distortion issues.
Innovation Solution
The implementation of a NFET or PFET current mirror circuit with a driver NFET, where the gate of the driver NFET is coupled to the drain of a PFET, and a sense NFET is gate-coupled to the high side driver NFET, along with capacitive feedback to control the edge rate of gate voltage transitions, allowing for fast charging during non-transition segments and controlled charging during transition segments to reduce EMI and maintain performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the output field effect transistors are turned on and off quickly to maintain amplifier performance, then the turn on and off time is reduced, but electromagnetic interference emissions increase
Solution Approach 1:
The gate drive strength is segmented into multiple levels using a multi-stage driver circuit. The first stage provides strong drive for fast switching, while subsequent stages provide progressively weaker drive to control the tail end of the transition, thereby reducing EMI without sacrificing overall switching speed.
Solution Approach 2:
The driver circuit dynamically adjusts its output impedance and drive strength during the switching transition. By using transistors with different gain values in series, the circuit automatically transitions from high-drive mode to low-drive mode as the gate voltage approaches its target, optimizing both speed and EMI performance.
2Object-generated harmful factors
If the output transition is reduced by weakening the gate drive strength, then the electromagnetic interference is reduced, but the turn on and off time increases resulting in performance degradation
Solution Approach 1:
The switching transition is divided into two phases: an initial fast-rising phase driven by the first transistor with higher gain, and a subsequent slower phase driven by the second transistor with lower gain. This segmentation allows the circuit to achieve both fast switching and reduced EMI tail.
Solution Approach 2:
Different portions of the gate voltage transition are driven by transistors with different characteristics. The initial portion uses a high-gain transistor for speed, while the tail portion uses a low-gain transistor for EMI control, applying local quality optimization to different segments of the same signal transition.
3Object-generated harmful factors
If the gate drive strength is reduced to unsharpen the edges, then the electromagnetic interference emissions are reduced, but distortion issues occur
Solution Approach 1:
The driver circuit dynamically transitions between different drive strength modes during the switching event. The first transistor provides strong drive for the main transition to avoid distortion, while the second transistor gently controls the tail end to reduce EMI, maintaining signal fidelity throughout the process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces output transition time, minimizing EMI and distortion while maintaining low delay and dead time, ensuring efficient and undistorted performance in amplifiers.
Implementation Method 1
capacitive feedback to control the edge rate of gate voltage transitions
Data Source
AI summary
An apparatus, comprising: a NFET current mirror having a first NFET and a second NFET; a PFET gate-coupled to the drain of the second NFET, wherein the PFET has a larger gain than the second NFET; a driver NFET having a gate that is coupled to the drain the PFET; wherein the second NFET is coupled through its source to the drain of the driver NFET.