Gate Drive IC GPM Signal Waveform Consistency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In large-sized flat panel displays, gate pulse delays occur due to longer gate lines, and existing gate pulse modulation techniques result in GPM signals with different waveforms caused by resistance differences between RE lines, leading to block dimming and gate pulse delay time variations across gate drive ICs.
Innovation Solution
The display device incorporates a configuration where all gate drive ICs generate GPM signals through a common first log line, eliminating the need for separate gate pulse modulators in each IC, thereby reducing area requirements and minimizing resistance-induced waveform differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate gate pulse modulators are incorporated in each gate drive IC, then gate pulse modulation can be performed locally, but resistance differences between RE lines cause waveform variations and block dimming
Solution Approach 1:
The patent merges the gate pulse modulation function from individual gate drive ICs into a single centralized gate pulse modulator. This modulator is positioned adjacent to the timing controller and generates a master GPM signal that is distributed to all gate drive ICs through a common RE line, eliminating waveform variations caused by distributed RE line resistance differences.
Solution Approach 2:
The patent introduces a master GPM signal as an intermediary that mediates between the timing controller and multiple gate drive ICs. This master signal serves as a common reference that all gate drive ICs use to generate their local GPM signals, ensuring waveform consistency across the display panel.
2Ease of operation
If gate pulse modulation is performed in each gate drive IC, then local control is achieved, but area requirements increase due to additional modulators
Solution Approach 1:
The patent extracts the gate pulse modulation function from within each gate drive IC and relocates it to a centralized position adjacent to the timing controller. This extraction eliminates the need for separate modulators in each gate drive IC, significantly reducing the total area required while maintaining the essential modulation functionality.
3Length of stationary object
If longer gate lines are used for large-sized panels, then display size increases, but gate pulse delay time increases
Solution Approach 1:
The patent changes the voltage waveform parameters of the gate pulse through modulation. By applying GPM that increases the voltage level during the fall time and creates different falling slopes, the patent compensates for the delay effects caused by longer gate lines, thereby maintaining proper timing characteristics despite increased line length.
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
A display device comprises: a display panel (100); and first and second gate drive ICs (GIC1, GIC2). The display panel (100) comprises: a first gate block in which a first gate line group is disposed; and a second gate block in which a second gate line group is disposed. The first gate drive IC (GIC1) generates a gate pulse that is provided to the first gate line group. The second gate drive IC (GIC2) generates a gate pulse that is provided to the second gate line group. The first gate drive IC (GIC1) comprises: a first gate pulse generator (400-1) for outputting a gate pulse (Gout) at a first voltage level; and a first gate pulse modulator (GPM1) for partially modulating the gate pulse (Gout).