Closed-Loop Gate-Drive Current Limiting for Power FET In-Rush Control
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Solution Overview
Problem
Existing FET-based DC-DC power converter architectures face challenges in avoiding excessive current in-rush during startup and maintaining charge balance, leading to potentially damaging current spikes and voltage spikes.
Innovation Solution
The implementation of circuits and methods that limit current through power FETs using a closed-loop feedback circuit and calibrated compensation circuit, independent of switching frequency, device mismatches, and PVT variations, to mitigate current spikes during soft-starts and dynamic charge balancing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FET-based DC-DC power converter architectures are used without sufficient guard circuitry, then the circuit can operate with simple structure, but excessive current in-rush occurs during startup causing potentially damaging current spikes and voltage spikes
Solution Approach 1:
The patent applies preliminary action by pre-charging the pump capacitors through a dedicated pre-charge path before normal power converter operation begins. This preliminary charging action ensures that when the power converter starts, the capacitors are already at the required voltage level, preventing excessive current in-rush and eliminating the need for complex external guard circuitry.
Solution Approach 2:
The patent introduces an intermediary pre-charge circuit that mediates between the power source and the pump capacitors. This intermediary circuit controls the charging process, allowing capacitors to be charged through a controlled path with appropriate current limiting, thereby protecting the power switches from damaging current spikes without requiring complex external protection circuitry.
2Productivity
If the power converter operates with high switching frequency to improve productivity, then the output voltage can be generated faster, but current spikes and voltage spikes increase causing reliability issues
Solution Approach 1:
The pre-charge circuit performs preliminary charging of pump capacitors before high-frequency switching begins. By ensuring capacitors are pre-charged to the appropriate voltage level, the system can immediately enter high-frequency operation without experiencing current or voltage spikes, thus achieving both high productivity and reliability.
Solution Approach 2:
The patent incorporates feedback mechanisms that monitor the charging status of pump capacitors and control the pre-charge path accordingly. This feedback ensures that capacitors are charged to the correct voltage level before normal operation, preventing voltage spikes during high-frequency switching while maintaining optimal productivity.
3Loss of energy
If the ON resistance of FET power switches is reduced to minimize power loss, then efficiency improves, but current in-rush increases during startup causing damaging voltage spikes
Solution Approach 1:
The patent segments the power conversion process into two distinct phases: a pre-charge phase with higher resistance to limit current, and a normal operation phase with low resistance for efficient power conversion. The pre-charge path uses a different resistance value than the main power switches, allowing current limiting during startup while maintaining low loss during normal operation.
Solution Approach 2:
The pre-charge circuit performs preliminary charging with controlled current before the main power switches operate at low resistance. This preliminary action ensures that capacitors are charged through a high-resistance path that limits current, after which the low-resistance power switches can operate efficiently without causing damaging current in-rush.
Data Source
AI summary
Circuits and methods that limit current through power FETs of power converter to reduce damaging current in-rush events, independent of switching frequency, device mismatches, and PVT variations. Embodiments utilize a closed-loop feedback circuit and/or a calibrated compensation circuit to regulate, substantially independent of frequency, the control voltage VGATE applied to a power FET gate. In a reduced gate-drive mode, connecting a feedback or compensation circuit to the gate of an LDO source-follower FET allows the gate voltage to be regulated to control the LDO output voltage to a final inverter coupled to the gate of a power FET so that VGATE is adjusted to provide a reduced gate-drive to the power FET; connecting to the output of the LDO allows the LDO output voltage to the final inverter to be directly regulated to adjust VGATE; connecting to the gate of the power FET allows VGATE to be directly set.