High Side Gate Drive Isolation for Semiconductor Testing

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Solution Overview

Problem

Testing electrical parameters such as breakdown voltage and leakage current in low side FETs within integrated semiconductor components is challenging due to the risk of damaging the driver circuit, especially when the drain-to-source voltage approaches the absolute maximum rating, making it difficult to perform tests like avalanche breakdown voltage, unclamped inductive switching, and Idss leakage tests accurately.

Innovation Solution

A semiconductor component design where the high side FET's source is connected to the low side FET's drain to form a switching node, with a gate drive circuit output electrically isolated from the switching node, allowing for the determination of breakdown voltage and leakage current without damaging the gate driver, and using a support structure like a copper leadframe for packaging.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the drain-to-source voltage of the low side FET is increased to test breakdown voltage and leakage current, then measurement precision is improved, but the driver circuit may be damaged due to exceeding absolute maximum ratings

Engineering Contradiction:
Improvebreakdown voltage and leakage current measurementVSAvoiddriver circuit safety
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The driver circuit is segmented into two independent power supply systems: a first power supply for normal operation and a second power supply for testing. This segmentation allows the low side FET to be tested at high voltages without exposing the driver circuit to damaging voltage levels, as each segment operates within its own voltage domain.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A second power supply acts as an intermediary between the test equipment and the driver circuit. It provides the high voltage needed for breakdown voltage and leakage current testing while isolating the driver circuit from these high voltage stresses through its own protection mechanisms and separate grounding.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If the low side FET is directly connected to the driver circuit for testing, then device complexity is reduced, but testing functional parameters becomes unsafe and difficult

Engineering Contradiction:
Improvecircuit configurationVSAvoidtesting functional parameters
Core Design Contradiction:
Device complexityVSDifficulty of detecting and measuring

Solution Approach 1:

The circuit is divided into two functional segments: a first power supply segment for normal driver operation and a second power supply segment for specialized testing. This segmentation enables safe testing of functional parameters like breakdown voltage and leakage current while maintaining a relatively simple overall device structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The driver circuit is designed with multi-functionality to support both normal operation mode (powered by first power supply) and testing mode (powered by second power supply). This universality allows the same circuit to serve dual purposes without requiring separate test equipment or complex reconfiguration.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8461670B2Semiconductor component and method of manufacture
Publication Date: 2013.06.11 SEMICON COMPONENTS IND LLC
  • US8461670B2 patent drawing
  • US8461670B2 patent drawing
  • US8461670B2 patent drawing

AI summary

A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component is configured to permit the determination of circuit parameters. A high side FET has a gate terminal coupled to an output terminal of a high side gate drive circuit, a drain terminal coupled for receiving an input voltage, and a source terminal coupled to the drain terminal of a low side FET. The gate terminal of the low side FET is coupled to the output terminal of low side drive circuit and the source terminal of the low side FET is coupled for receiving a source of operating potential. The high side gate drive circuit has a bias terminal coupled for receiving a floating potential where the bias terminal is electrically isolated or decoupled from the commonly connected source and drain terminals of the high side FET and the low side FET, respectively.