Gate Drive Inverter Circuit for Low Through-Current Displays
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Solution Overview
Problem
Existing gate driven on array (GOA) technology experiences excessive through-current between VGH and VGL, leading to voltage level fluctuations and excessive heating, particularly in displays with more than 1000 stages, which hinders narrow-bezel design.
Innovation Solution
An inverter circuit with a first and second transistor configuration, where the second transistor acts as a pull-up transistor, reducing its on-current through adjustable control voltage, and an adjusting sub-circuit to manage the on-degree, minimizing through-current and maintaining stable voltage levels without enlarging the first transistor size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the first transistor size is increased to reduce through-current, then the through-current between VGH and VGL is reduced, but the device area and manufacturing complexity increase
Solution Approach 1:
The pull-up function is segmented from the first transistor and implemented by a separate second transistor. This segmentation allows independent optimization of the first transistor for signal driving while the second transistor handles the pull-up current control, reducing the need to enlarge the first transistor and thereby reducing through-current without increasing its area.
Solution Approach 2:
The second transistor acts as an intermediary component between the high-level voltage source and the inverted-signal output terminal. It mediates the current flow by providing a controlled pull-up path, which reduces the through-current burden on the first transistor and allows for smaller device area while maintaining current control.
2Adaptability or versatility
If the number of array units is increased to more than 1000 stages, then the functionality and coverage are improved, but the accumulated through-current affects voltage levels and causes excessive heating
Solution Approach 1:
By segmenting the inverter circuit into two transistors with distinct functions, the through-current is reduced at each stage. When cascaded into more than 1000 stages, this per-stage current reduction prevents accumulated through-current from affecting VGH and VGL voltage levels and causes excessive heating, thereby enabling high-stage functionality without thermal issues.
Solution Approach 2:
The invention changes the electrical parameters of the inverter circuit by introducing a second transistor with specific on-impedance characteristics. This parameter change reduces the through-current at each stage, allowing the system to scale to more than 1000 stages without the accumulated current causing voltage level degradation or excessive heating.
3Speed
If the second transistor on-current is increased to improve pull-up capability, then the pull-up speed is improved, but the through-current and heating increase
Solution Approach 1:
The second transistor's on-current is dynamically controlled through its control terminal, allowing the pull-up speed to be optimized without permanently increasing the through-current. The dynamic control enables fast pull-up when needed while maintaining lower current during normal operation, thus improving speed without proportionally increasing heating.
Solution Approach 2:
By changing the control voltage applied to the second transistor's control terminal, the on-current can be adjusted to achieve optimal pull-up speed. This parameter control allows the system to maintain lower through-current compared to simply increasing the transistor size, thereby reducing heating while still providing adequate pull-up capability.
Data Source
AI summary
An inverter circuit, a gate drive circuit, and a display device are provided in the disclosure. The inverter circuit includes an inverted-signal output terminal, a first transistor, and a second transistor. A first connection terminal of the first transistor is electrically connected to the inverted-signal output terminal, a second connection terminal of the first transistor is configured to receive a first low-level voltage, and a control terminal of the first transistor is configured to receive an input signal. A first connection terminal and a first control terminal of the second transistor are both configured to receive a high-level voltage, and a second connection terminal of the second transistor is electrically connected to the inverted-signal output terminal. When the input signal is at a low level, the inverted-signal output terminal outputs a high-level signal. When the input signal is at a high level, the inverted-signal output terminal outputs a low-level signal.