Cascaded Gate Drive Circuit for Multi-Pulse Display Panel Timing
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Solution Overview
Problem
Conventional gate drive circuits are limited in providing the required number and timing of gate control signals for pixel circuits, which restricts their ability to effectively drive the pixel circuit and meet the demands of modern display panel technology.
Innovation Solution
A gate drive circuit with cascaded units, including a stage transmission signal selection circuit, pull-up control circuit, pulse number reduction circuit, first and second output stages, and specific transistor configurations, is designed to generate more pulses in a frame, enhancing the capability to drive pixel circuits by optimizing the output stages and transistor ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional gate drive circuit is used, then device complexity is reduced, but the number and timing of gate control signals cannot meet pixel circuit requirements
Solution Approach 1:
The gate drive circuit is divided into multiple cascaded gate drive units, where each unit can independently generate and output gate control signals. This segmentation allows the system to provide multiple pulses per frame by cascading multiple units, thereby enhancing adaptability without requiring a complete redesign of the entire circuit.
Solution Approach 2:
The gate drive circuit incorporates dynamic control mechanisms including a stage transmission signal selection circuit that can selectively transmit signals based on timing requirements, and a pulse number reduction circuit that dynamically adjusts the number of pulses output. These dynamic elements enable the circuit to adapt to varying pixel circuit requirements while maintaining manageable complexity.
2Productivity
If more pulses are generated in a frame, then pixel circuit driving capability is improved, but circuit complexity increases
Solution Approach 1:
The gate drive unit incorporates a pull-up control circuit that pre-charges nodes to appropriate potentials before signal transmission. This preliminary action ensures that when pulses are generated, they have the correct voltage levels and timing characteristics, enabling multiple pulses per frame without requiring complex real-time adjustment mechanisms.
Solution Approach 2:
The stage transmission signal selection circuit acts as an intermediary between the internal pulse generation mechanism and the external output. It selectively transmits or blocks signals based on timing requirements, allowing the circuit to generate multiple pulses per frame while maintaining controlled complexity through this mediating layer.
3Ease of manufacture
If three transistors of same channel type are used, then manufacturing process is simplified, but transistor configuration complexity increases
Solution Approach 1:
The gate drive unit is designed to use three transistors of the same channel type (all P-channel or all N-channel). This homogeneity simplifies the manufacturing process by reducing the need for mixed transistor types and their associated fabrication variations. The patent achieves this by carefully designing the transistor connections and control signals to function correctly with uniform transistor characteristics.
Solution Approach 2:
While using symmetric transistor types, the patent employs asymmetric connection configurations and control signal timing to achieve the desired functionality. The transistors are connected in non-identical arrangements with different gate control signals applied at different times, allowing complex signal generation while maintaining manufacturing simplicity through transistor uniformity.
Data Source
AI summary
A gate drive circuit includes a plurality of gate drive units. Each of the gate drive units includes a stage transmission signal selection circuit, a pull-up control circuit, a pulse number reduction circuit, a first inversion circuit, a first output stage, and a second output stage, and can output a second gate control signal with a greater number of pulses and a first gate control signal with a less number of pulses. At least one of the stage transmission signal selection circuit, the first inversion circuit or the second output stage includes three transistors with the same channel type.