Gate Drive Circuit for Narrow Bezel Displays
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Solution Overview
Problem
The existing gate drive circuits in display devices suffer from DC gate bias stress, which causes threshold voltage shifts in transistors, reducing the on-current and affecting reliability, especially at high temperatures, making it difficult to achieve a narrow bezel due to the need for larger transistors to mitigate this stress.
Innovation Solution
A gate drive circuit design that includes monitoring transistors and comparators to sense and compensate for threshold voltage shifts by varying charging voltages for Q and QB nodes, using different gate-low voltages to apply negative bias stress and reduce positive stress on transistors, allowing for reduced transistor size and bezel width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel size of transistors is increased to reduce DC gate bias stress effects, then the transistor reliability is improved, but the transistor size increases leading to wider bezel
Solution Approach 1:
The patent applies preliminary action by pre-charging the Q node to a first voltage level before the switching operation. This preliminary charging reduces the stress on the transistor during subsequent operations, allowing for smaller transistor sizes while maintaining reliability. The pull-up transistor charges the Q node to this first voltage in advance, preparing the circuit state to minimize DC gate bias stress effects.
Solution Approach 2:
The patent changes voltage parameters by introducing a first voltage (higher than VDD) for charging the Q node, in addition to the standard VDD voltage. This parameter change allows the transistor to operate with reduced stress by controlling the voltage levels more precisely, enabling smaller transistor sizes while maintaining the required reliability against DC gate bias stress.
2Reliability
If larger transistors are used to mitigate DC gate bias stress, then the threshold voltage shift is reduced, but the bezel width increases
Solution Approach 1:
The circuit performs preliminary charging of the Q node to a first voltage level before the main switching operation. This preliminary action stabilizes the transistor operating conditions and reduces threshold voltage shift during operation, allowing for smaller transistor sizes that fit within narrower bezel constraints.
Solution Approach 2:
The patent implements periodic action through the sequential charging and discharging cycles of the Q node. The Q node is periodically charged to the first voltage by the pull-up transistor and then discharged by the pull-down transistor, creating a rhythmic operation that prevents sustained DC gate bias stress, thereby reducing threshold voltage shift and enabling smaller transistor sizes.
3Ease of operation
If DC voltage is continuously applied to the transistor gate to maintain operation, then the transistor remains in on-state, but DC gate bias stress increases causing threshold voltage shift
Solution Approach 1:
The patent applies periodic action by using pulsed voltage application to the Q node instead of continuous DC voltage. The Q node is charged to a first voltage level and then discharged, creating periodic on/off cycles that maintain transistor operation while preventing sustained DC gate bias stress. This periodic operation maintains ease of operation while improving threshold voltage stability.
Solution Approach 2:
The patent introduces dynamics by transitioning from static DC voltage application to dynamic pulsed voltage application. The Q node voltage dynamically switches between the first voltage level and lower levels, allowing the transistor to operate effectively while avoiding the continuous stress conditions that cause threshold voltage shift. This dynamic approach maintains operational ease while improving reliability.
Data Source
AI summary
A gate drive circuit and a display device are provided. The gate drive circuit comprises: a first stage that outputs a first gate pulse at a first output terminal by increasing a voltage at the first output terminal when a first Q node is charged in response to receiving a first carry signal at a first start terminal, and decreasing the voltage at the first output terminal when a first QB node is charged; and a second stage that outputs a second gate pulse at a second output terminal and outputs a second carry signal at a third output terminal by increasing voltages at the second and third output terminals when a second Q node is charged in response to receiving the first carry signal at a second start terminal, and decreasing the voltages at the second and third output terminals when a second QB node is charged.