Gate Drive Circuit Noise Reduction via Phase-Shifted Shift Register
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Amorphous silicon gate (ASG) technology in display devices generates noise due to continuously changing clock signals, which reduces display quality and requires a method for improved driving reliability of gate lines, especially when the gate drive part operates at high temperatures.
Innovation Solution
A method and gate drive circuit that utilize a shift register with multiple stages connected in series, including pull-up, holding, and pull-down parts, to manage node signals and clock signals effectively, maintaining signals at appropriate voltage levels to minimize noise and prevent voltage stress, thereby enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a shift register with continuously changing clock signals is used to drive gate lines, then the gate drive circuit can be simplified and manufactured at lower cost, but noise is generated that reduces display quality
Solution Approach 1:
The shift register is divided into multiple stages (first stage, second stage, third stage) with each stage controlling different gate lines. This segmentation allows the clock signal to be divided into phases, where each phase drives a specific stage, reducing the continuous noise generation while maintaining the simplified ASG structure.
Solution Approach 2:
The patent implements periodic action by using phase-shifted clock signals to drive different stages of the shift register in sequence. The first clock signal drives the first stage, the second clock signal (phase-shifted) drives the second stage, and the third clock signal drives the third stage. This periodic driving pattern reduces noise by avoiding simultaneous switching of all stages.
2Productivity
If the gate drive circuit operates at high temperatures for extended periods, then productivity is maintained, but noise increases and reliability decreases
Solution Approach 1:
The patent applies preliminary action by maintaining node signals at predetermined voltage levels (high or low) before the actual gate driving occurs. The first node signal is maintained at a high level during a first period, and the second node signal is maintained at a low level during a second period, preparing the circuit state before the next driving cycle. This preliminary stabilization prevents noise generation even at high temperatures.
Solution Approach 2:
The patent changes the voltage parameters of node signals to maintain stability at high temperatures. By keeping the first node signal at a high level and the second node signal at a low level during specific periods, the circuit parameters are optimized to prevent thermal noise while maintaining driving speed and reliability.
3Device complexity
If node signals are not maintained at stable voltage levels, then the circuit is simpler to control, but voltage stress causes characteristic changes and reduces reliability
Solution Approach 1:
The patent implements feedback by using the state of node signals to control the timing of subsequent driving operations. The first node signal is maintained at a high level during a first period, and the second node signal is maintained at a low level during a second period, creating a feedback mechanism that stabilizes the circuit state and prevents voltage stress-induced characteristic changes.
Data Source
AI summary
A pull-up driving part maintains a signal of a first node at a high level by receiving a turn-on voltage in response to one of a previous stage or a vertical start signal. A pull-up part outputs a clock signal through an output terminal in response to the signal of the first node. A first holding part maintains a signal of a second node at a high level or a low level when the signal of the first node is respectively low or high. A second holding part maintains the signal of the first node and a signal of the output terminal at a ground voltage in response to the signal of the second node or a delayed and inverted clock signal.