Gate Drive Apparatus for Parallel Switching Element Synchronization
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Solution Overview
Problem
In switch circuits with multiple MOS transistors connected in parallel, current imbalance occurs due to differing transistor characteristics, leading to excessive heating and potential damage of one transistor when turned on and off repeatedly, as only one transistor handles the majority of the current.
Innovation Solution
A gate drive apparatus that includes a switching time measurement unit to calculate delay times for each transistor, time difference calculation units to adjust pulse widths, and auxiliary switches to synchronize the turning on and off of transistors, ensuring simultaneous operation and reducing current imbalance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple MOS transistors are connected in parallel to increase current capacity, then the overall current capacity increases, but current imbalance occurs causing excessive heating and potential damage to individual transistors
Solution Approach 1:
The gate drive apparatus performs preliminary measurement of switching timing characteristics for each transistor before operation. Based on these measurements, it pre-calculates and stores delay time adjustments that will be applied during operation to synchronize switching times and prevent current imbalance
Solution Approach 2:
The system measures the actual switching timing of each transistor and uses this feedback information to calculate appropriate delay time adjustments. This closed-loop approach ensures that timing corrections are based on real performance data, optimizing current distribution across all transistors
2Ease of operation
If gate voltage is applied simultaneously to all parallel-connected transistors, then the control is simple, but transistors with different characteristics turn on at different times causing current concentration in single transistor
Solution Approach 1:
The gate drive apparatus applies different delay time adjustments to each transistor's gate signal based on its individual switching characteristics. This localized customization of control parameters ensures that each transistor switches at the appropriate time relative to others, achieving simultaneous effective switching despite manufacturing variations
Solution Approach 2:
The system modifies the timing parameter (delay time) of gate signals individually for each transistor. By changing these temporal parameters based on measured characteristics, the system synchronizes switching events across all parallel transistors while maintaining simple overall control architecture
Data Source
AI summary
A gate drive apparatus including a switching time measurement unit that calculates a first or second delay time that is between a time at which a rising edge or a falling edge of a gate voltage is applied to the gate terminal of a switching element and a time at which the switching element is turned on or off. The gate drive apparatus further includes first and second time difference calculation units that respectively calculate first and second time differences, first and second pulse generation units that respectively generate first and second pulses having pulse widths that respectively match the first and second time differences, and first and second auxiliary switches that are configured to, upon receiving a first pulse or a second pulse, supply a source current to the gate terminal that corresponds to the first pulse, or absorb a sink current from the gate terminal that corresponds to the second pulse.