Gate Drive Circuit Pulse-Width Control Across Refresh Frequencies
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Solution Overview
Problem
Existing gate drive circuits in frequency division displays face issues with narrow pulse widths during refresh frequency switching, leading to reduced charging time and display abnormalities.
Innovation Solution
A gate drive circuit with shift register groups, each including N adjacent shift registers, featuring a first output stage and a frequency division control module, adjusts pulse widths using control signals with different phases to maintain consistent pulse widths across varying refresh frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If frequency division display is implemented to support different refresh frequencies, then adaptability is improved, but pulse width becomes narrow and charging time is reduced
Solution Approach 1:
The gate drive circuit dynamically adjusts the output signal characteristics based on refresh frequency requirements. The circuit switches between different operating modes (first mode for normal refresh, second mode for low refresh) to maintain appropriate pulse widths across different display scenarios, making the system adaptive without sacrificing signal quality
Solution Approach 2:
The invention changes the operating parameters of the gate drive circuit based on detected refresh frequency. When low refresh frequency is detected, the circuit transitions to a second output mode with modified signal characteristics including extended pulse width, ensuring sufficient charging time while maintaining adaptability to different refresh rates
2Use of energy by moving object
If refresh frequency is reduced for power saving, then energy consumption is reduced, but pulse width becomes insufficient leading to display abnormalities
Solution Approach 1:
The gate drive circuit incorporates feedback mechanisms to detect the actual refresh frequency being used. Based on this feedback, the circuit automatically adjusts its output mode to ensure reliable operation. When low refresh mode is detected, the circuit activates compensation mechanisms to maintain display reliability despite reduced operating frequency
Solution Approach 2:
The circuit dynamically adapts its behavior based on the operating conditions. It switches between normal operating mode and compensated operating mode depending on refresh frequency, allowing power savings at low refresh rates while maintaining display reliability through automatic mode transition
3Duration of action of moving object
If gate drive signal pulse width is extended to ensure charging time, then charging time is improved, but circuit complexity increases
Solution Approach 1:
The gate drive circuit is designed with multi-functionality, where a single circuit structure can operate in multiple modes (normal mode and low refresh mode). By using the same hardware resources for different functions and modes, the circuit achieves extended charging time capability without proportionally increasing complexity
Solution Approach 2:
Instead of adding complex hardware to extend pulse width, the invention changes the operational parameters and timing characteristics of the existing circuit. The same circuit structure produces different output characteristics based on the operating mode, achieving extended charging time through parameter adjustment rather than structural complexity
Data Source
AI summary
A gate drive circuit and a display panel. The gate drive circuit includes one or more shift register groups. Each of the shift register groups includes N shift adjacent registers that output in sequence, with N being an integer greater than or equal to 3. Each of the shift registers includes a first output stage and a frequency division control module. The first output stage is configured to output a gate drive signal. The frequency division control module is configured to control outputting of the gate drive signal based on a refresh frequency. A control end of each frequency division control module in each of the shift register groups receives a control signal with a different phase and a same frequency, respectively, to adjust a pulse width of the gate drive signal and maintain a same pulse width at different refresh frequencies.