Non-Overlapping Gate Drive Circuit With PVT-Tracked Delay
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Solution Overview
Problem
Existing gate drive circuits for power stages in integrated circuits face challenges in efficiently managing break-before-make operations under varying process, voltage, and temperature conditions, particularly due to the large area consumption of high voltage level shifters and the need for precise timing to prevent simultaneous activation of transistors.
Innovation Solution
A non-overlapping signal generator is implemented in the gate drive circuitry, comprising a PDRV circuit and an NDRV circuit with delay-tracking elements to ensure that the PMOS and NMOS transistors in an H-bridge circuit operate without overlap, using area-efficient designs that account for PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If high voltage level shifters are used to translate signals from low voltage to high voltage, then voltage level translation is achieved, but circuit area increases
Solution Approach 1:
The patent combines the level shifting function with the delay generation function into a single integrated circuit block. The same transistor network that performs voltage level translation also generates the required delay for break-before-make operation, eliminating the need for separate high voltage level shifter circuits and reducing overall circuit area.
Solution Approach 2:
The circuit performs multiple functions simultaneously: it translates voltage levels from low to high, generates precise delays for timing control, and ensures break-before-make operation. This multi-functionality reduces the total number of components and circuit area required compared to using separate dedicated circuits for each function.
2Reliability
If delay elements are added to ensure break-before-make operation, then timing precision is improved, but circuit complexity increases
Solution Approach 1:
The delay generation is merged with the level shifting operation using the same transistor network. The delay is generated as a natural byproduct of the level shifting process through carefully designed signal paths and transistor timing characteristics, rather than adding separate delay elements that would increase circuit complexity.
Solution Approach 2:
The circuit preliminarily establishes the timing relationship between complementary transistor gates through the level shifting process itself. The delay required for break-before-make is built into the signal path design, ensuring proper timing before the actual switching operation occurs, without requiring additional complex delay control circuitry.
3Ease of operation
If separate gate drive circuits are used for PMOS and NMOS transistors, then independent control is achieved, but area consumption increases
Solution Approach 1:
The patent uses a single integrated circuit block that generates gate drive signals for both PMOS and NMOS transistors. The circuit internally manages independent control of each transistor through separate signal paths within the same block, maintaining independent control capability while sharing common infrastructure to reduce area consumption.
Solution Approach 2:
The gate drive circuit block serves multiple purposes: it translates voltage levels, generates timing delays, controls both PMOS and NMOS transistors independently, and ensures break-before-make operation. This multi-functionality allows independent control of transistors without requiring separate dedicated circuits for each function, thereby reducing overall area.
Data Source
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AI summary
Certain aspects of the present disclosure generally relate to a power stage (100). The power stage generally includes a first transistor (122), a second transistor (120) having a drain coupled to a drain of the first transistor, a first gate drive circuit (102) coupled between an input node of the power stage (105) and a gate of the first transistor (122), and a second gate drive circuit (104) having a first signal path (slow path: 140) coupled between the input node and a gate of the second transistor. In certain aspects, the second gate drive circuit comprises a plurality of buffers (180, 182, 184, 186) in the first signal path, and a plurality of electronic devices (170, 172, 196, 198) coupled to the plurality of buffers and configured to apply a delay associated with driving the gate of the second transistor (120) to track a delay associated with driving the gate of the first transistor (122) via the first gate drive circuit (102).