Gate Drive Circuit Reset Control for Display Refresh Rate
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Solution Overview
Problem
Display panels with existing gate drive circuits have a low display refresh rate due to the need for virtual shift registers, which increase storage requirements and delay, reducing efficiency and increasing costs.
Innovation Solution
A gate drive circuit with cascaded shift registers, including input, reset, and output sub-circuits, where the reset control sub-circuit connects different start signal ends to allow simultaneous charging and resetting, eliminating the need for virtual shift registers and optimizing resource use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If virtual shift registers are used in the gate drive circuit, then the circuit can reset the first node, but the storage requirements and display delay increase, reducing the display refresh rate
Solution Approach 1:
The patent extracts and removes the virtual shift register component from the gate drive circuit. By eliminating this redundant component, the circuit achieves the reset function through alternative means (using the second cascaded input end connected to different start signal ends) while reducing storage requirements and display delay, thereby improving the display refresh rate
Solution Approach 2:
The patent makes the second cascaded input end serve multiple functions: it can receive signals from different start signal ends and enable the reset function without requiring a dedicated virtual shift register. This multi-functional design reduces the overall circuit complexity and storage requirements while maintaining the necessary reset capability
2Reliability
If virtual shift registers are used in the gate drive circuit, then the reset function is achieved, but the storage resources and cost increase
Solution Approach 1:
The patent removes the virtual shift register component that consumes storage resources. The reset function is achieved through the second cascaded input end connected to different start signal ends, eliminating the need for additional storage elements and reducing both storage resources and circuit cost
Solution Approach 2:
The patent merges the reset function with the existing shift register structure by utilizing the second cascaded input end. This integration eliminates the need for separate virtual shift registers and their associated storage resources, achieving functionality consolidation and resource optimization
3Device complexity
If the first node is charged and reset sequentially in the same drive unit, then the circuit operation is simple, but the display refresh rate is limited
Solution Approach 1:
The patent segments the charging and resetting operations by connecting them to different start signal ends through the reset control sub-circuit. This allows charging (through the first cascaded input end) and resetting (through the second cascaded input end) to occur in parallel across different drive units, increasing the display refresh rate while maintaining manageable circuit complexity through modular organization
4Productivity
If different start signal ends are connected to the first cascaded input end of different drive units, then parallel operation is enabled, but the reset control becomes complex
Solution Approach 1:
The patent makes the second cascaded input end a universal interface that can be connected to different start signal ends (STV1, STV2, STV3, etc.) depending on the drive unit configuration. This universal design enables parallel operation across multiple drive units while keeping the reset control logic relatively simple, as the same circuit structure adapts to different start signal configurations
Data Source
AI summary
A display panel, a gate drive circuit and a driving method thereof. The gate drive circuit includes drive units. A first cascaded input end OUT(n−1) of a first shift register (100) of each of the drive units is connected to a different start signal end STV; a plurality of drive units in the drive units include a reset control sub-circuit (9), where the reset control sub-circuit (9) is connected with a second cascaded input end OUT(n+1) of a last shift register (100) and one or more start signal ends STV, and is configured to control an electric potential of the second cascaded input end OUT(n−1) according to an electric potential of the one or more start signal ends STV.