Gate Drive Timing to Prevent MOSFET Self-Turn-On
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Solution Overview
Problem
Existing gate drive circuits for high-side and low-side transistors in switching power supply devices face challenges in preventing self-turn-on due to high slew rates of voltage changes, which can lead to inefficiencies and reduced performance.
Innovation Solution
The proposed solution involves a gate drive circuit with a high-side pre-driver and a low-side pre-driver, where a delay is introduced in the gate signals to control the switching of high-side and low-side transistors, thereby managing the slew rate and preventing self-turn-on.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the slew rate of voltage change at the node is high, then the switching speed is improved, but the Vgs of the transistor which is turned off is raised, causing self-turn-on
Solution Approach 1:
The gate drive circuit applies a negative voltage to the gate of the transistor before the voltage change at the node occurs, preemptively ensuring the transistor remains off. This preliminary action counteracts the potential self-turn-on effect caused by high slew rate voltage changes, allowing fast switching without compromising reliability
2Reliability
If a delay is introduced in the gate signals to control switching, then self-turn-on is prevented, but the switching response time increases
Solution Approach 1:
The gate drive circuit dynamically changes the voltage parameter applied to the transistor gate, using negative voltage during critical switching transitions and standard drive voltage during normal operation. This parameter variation enables reliable self-turn-on prevention while minimizing the impact on switching response time
Data Source
AI summary
A high-side pre-driver includes a first high-side transistor and a second high-side transistor, a low-side pre-driver includes a third high-side transistor and a fourth high-side transistor and a delay is provided in at least one of a time period between a first gate signal configured to turn on the first high-side transistor and a second gate signal configured to turn on the second high-side transistor and a time period between a third gate signal configured to turn on the third high-side transistor and a fourth gate signal configured to turn on the fourth high-side transistor.