Gate Drive Signal Filter for Display Clock Noise Reduction
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Solution Overview
Problem
Current gate drive circuits in display apparatuses generate noise due to direct transmission of clock signals to output transistors, which affects the normal operation and output stages.
Innovation Solution
A gate drive unit is introduced, comprising a shift register and a signal filter that controls the transmission of clock signals, disconnecting them during reset stages to prevent noise generation, and includes pre-charging, reset, and output circuits to manage signal potentials effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If clock signals are directly transmitted to output transistors, then the gate drive circuit can operate simply, but noise is generated during reset stages affecting normal operation
Solution Approach 1:
The patent introduces a signal filter as an intermediary component between the clock signal terminal and the output transistor. This filter includes a capacitor connected in parallel with the output transistor, which acts as a mediator to block high-frequency noise signals from reaching the output transistor while allowing the normal clock signal to pass through, thereby eliminating noise without complicating the overall circuit structure
Solution Approach 2:
The patent extracts and removes the harmful noise component from the clock signal by using the signal filter. The capacitor in the filter captures and stores the high-frequency noise, separating it from the useful clock signal, and prevents it from affecting the output transistor during reset stages
2Duration of action of stationary object
If clock signals are transmitted during reset stages, then the gate drive unit can maintain continuous operation, but noise is generated that disrupts normal output stages
Solution Approach 1:
The signal filter serves as a mediator that allows the clock signal to pass through during normal operation while blocking noise during reset stages. The capacitor in the filter maintains the continuity of the clock signal transmission while simultaneously protecting the output transistor from noise interference, ensuring reliable operation throughout all phases
3Object-generated harmful factors
If the signal filter is added to block noise, then noise is reduced, but the device complexity increases
Solution Approach 1:
The signal filter is implemented as a simple intermediary component with minimal structural complexity. The capacitor-based filter adds only a single element to the circuit while effectively blocking noise, making the increase in device complexity negligible compared to the significant reduction in noise interference
Solution Approach 2:
The noise is extracted and isolated from the clock signal through the signal filter, allowing the main circuit to remain simple. By removing only the harmful noise component rather than redesigning the entire circuit, the patent achieves noise reduction with minimal impact on overall device complexity
Data Source
AI summary
The present disclose is related to a gate drive unit. The gate drive unit may include a shift register; and a signal filter. The signal filter may respectively connect to a clock signal terminal, a filter output terminal, an input terminal and a reset terminal. The signal filter may be configured, under control of an effective signal provided by the input terminal, to transmit a clock signal of the clock signal terminal to the filter output terminal after the input terminal stops providing the effective signal and before the reset terminal provides an effective signal and, under control of an effective signal provided by the reset terminal, to disconnect the clock signal terminal and the filter output terminal.