Gate Drive Apparatus Signal Line Reduction
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Solution Overview
Problem
The existing gate drive apparatus requires 10 signal lines to operate, leading to wider edge frames and increased raw material consumption in display panels, making the display apparatus costly.
Innovation Solution
A gate drive apparatus with N shift register units, where signal connections and clock signals are optimized to reduce the number of signal lines needed, allowing each shift register unit to use clock signals as scan signals or reset signals as low-level signals, thereby omitting unnecessary signal links.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 10 signal lines are used to drive the gate drive apparatus, then the apparatus can operate reliably, but the edge frame width increases and raw material consumption increases
Solution Approach 1:
The patent combines multiple signal functions into fewer signal lines. Specifically, the clock signal is reused as both a clock signal and a forward scan signal, and the low level signal is reused as both a low level signal and a backward scan signal. This merging of functions reduces the total number of signal lines from 10 to 8, thereby reducing edge frame width and raw material consumption while maintaining reliable operation.
Solution Approach 2:
The patent implements multi-functionality by designing signal lines that perform multiple roles. The clock signal terminal provides both clocking function and forward scanning function, while the low level signal terminal provides both low level reference and backward scanning function. This universal usage of signal lines eliminates the need for separate dedicated scan signal lines, reducing material consumption.
2Reliability
If 10 signal lines are used to drive the gate drive apparatus, then the apparatus can operate reliably, but the manufacturing cost increases
Solution Approach 1:
By merging the clock signal with the forward scan signal function and the low level signal with the backward scan signal function, the patent reduces the number of signal lines required. This reduction directly decreases the complexity of the display panel structure, reduces raw material consumption, and lowers manufacturing costs while preserving the reliable operation of the gate drive apparatus.
3Device complexity
If clock signals are used as scan signals and reset signals as low-level signals, then the number of signal lines is reduced, but signal timing and overlap requirements must be met
Solution Approach 1:
The patent incorporates preliminary timing design by ensuring that the overlap period between adjacent clock signals is sufficient to allow the transistor gate to charge to the required voltage level before the next signal transition. This pre-planned timing overlap ensures that signal integrity is maintained despite the reduced number of signal lines, meeting manufacturing precision requirements.
Data Source
AI summary
Embodiments of the invention provide a gate drive apparatus and a display apparatus. With the gate drive apparatus, a clock signal is used in place of a forward scan signal and/or a clock signal is used in place of a backward scan signal and/or a reset signal and a first initial trigger signal (or a second initial trigger signal) are used in place of a low level signal and/or the same signal is used as a first initial trigger signal and a second initial trigger signal to thereby reduce the number of transmission lines for signals driving the gate drive apparatus.