Gate Drive Apparatus Staggering Initialization Current Surge
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Solution Overview
Problem
Liquid crystal displays (LCDs) face high current surges during startup and shutdown, leading to potential damage to power supply chips and connection wires due to simultaneous current impacts from all gate lines.
Innovation Solution
A gate drive device that divides gate lines into groups and staggers the initialization and discharging operations using multiple control signals with time delays to prevent overlapping current impacts during startup and shutdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all gate lines are initialized to low voltage simultaneously during startup, then all pixel rows are initialized to non-scanning state, but the current of power supply voltage terminal becomes very large in a moment
Solution Approach 1:
The gate lines are divided into multiple groups, and the initialization operation is segmented across different time periods. Each group of gate lines is initialized in sequence rather than simultaneously, which distributes the current demand over time and reduces the peak current surge on the power supply voltage terminal.
Solution Approach 2:
The gate drive device predicts or pre-determines the initialization timing of different gate line groups and schedules them in advance to avoid simultaneous current draw. By planning the initialization sequence beforehand, the system prevents overlapping current impacts before they occur.
2Reliability
If all gate lines are set to high voltage simultaneously during shutdown, then all pixel rows are put in scanned state for quick discharging, but the current of power supply voltage terminal becomes very large in a moment
Solution Approach 1:
During shutdown, the gate lines are divided into multiple groups and the voltage switching operation is segmented across different time periods. Each group is switched to high voltage in sequence, distributing the current demand and reducing the peak current surge on the power supply voltage terminal while still achieving complete discharge of all pixels.
Solution Approach 2:
The gate drive device pre-determines the shutdown timing for different gate line groups and schedules them in advance. By planning the sequential switching sequence beforehand, the system avoids simultaneous current draw during shutdown while ensuring all pixels are properly discharged.
3Productivity
If multiple gate drivers are turned on simultaneously, then all gate lines are activated at once, but the impact currents overlap and increase total current impact
Solution Approach 1:
The gate drivers are divided into multiple groups corresponding to different time periods. Each gate driver group is activated in sequence rather than simultaneously, which maintains overall initialization productivity while preventing overlap of impact currents. The segmentation ensures that current impacts are distributed temporally.
Solution Approach 2:
The gate drive device employs periodic or sequential activation of gate driver groups with different time delays. This periodic action pattern ensures that impact currents from different gate drivers do not overlap, reducing total current impact while maintaining efficient initialization through coordinated sequencing.
4Device complexity
If a single control signal controls all gate drivers, then the control circuit is simple, but all gate drivers operate simultaneously causing current surge
Solution Approach 1:
The control circuit is segmented into multiple control signal generating modules, each responsible for controlling a specific group of gate drivers. This segmentation adds some complexity but enables temporal distribution of gate driver activation, reducing current surge. The modular structure balances complexity management with current surge mitigation.
Solution Approach 2:
The control circuit introduces time delay mechanisms as intermediary elements between the control signal generating modules and the gate drivers. These intermediaries sequence the activation of gate drivers, preventing simultaneous operation and current surge, while the overall control architecture remains manageable through modular design.
Data Source
Figure 1A~1B
Figure 2
Figure 3~4
AI summary
Disclosed are a gate driving apparatus (200) for a pixel array and a driving method therefor. The pixel array comprises N gate lines. The gate driving apparatus (200) comprises: a plurality of gate drivers (221, 222,..., 22(n-1), 22n), wherein the N gate lines are divided into a plurality of groups, each group comprises a plurality of gate lines, each gate driver (221, 222,..., 22(n-1), 22n) corresponds to the plurality of groups on a one-to-one basis, and each gate driver (221, 222,..., 22(n-1), 22n) is used for generating a gate driving signal for the plurality of gate lines in the group corresponding thereto; and a driver control module (210) which is used for generating a plurality of driver control signals (XON1, XON2,..., XON(n-1), XONn), the plurality of driver control signals (XON1, XON2,..., XON(n-1), XONn) corresponding to the plurality of gate drivers (221, 222,..., 22(n-1), 22n) on a one-to-one basis, and a state switch between any two driver control signals among the plurality of driver control signals (XON1, XON2,..., XON(n-1), XONn) has at least a difference of a first time, wherein under the control of the plurality of driver control signals (XON1, XON2,..., XON(n-1), XONn), the plurality of gate drivers (221, 222,..., 22(n-1), 22n) are switched from a first state to a second state in sequence, and each gate driver (221, 222,..., 22(n-1), 22n) generates gate driving signals in the same phase at the same time for the plurality of gate lines in the group corresponding thereto in the second state.