Gate Drive Circuit Transistor Channel Length Ratio
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Solution Overview
Problem
Existing gate drive circuits in display technologies face instability due to parasitic capacitance in transistors, affecting the potential of the pull-up node and overall performance.
Innovation Solution
A gate drive circuit with multi-stage cascaded units, including pull-up control, output, pull-down, and pull-down maintain modules, where the ratio of the channel length of the pull-up control transistor to the scan signal output transistor is between 1:8 and 1:12, optimizing the potential of the pull-up node, switching time, charging rate, and capacitance values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistors are used in gate drive units, then the circuit can be manufactured with standard processes, but parasitic capacitance affects the pull-up node potential and reduces circuit stability
Solution Approach 1:
The patent changes the channel length parameter of the pull-up control transistor to be 1/8 to 1/12 of the scan signal output transistor's channel length. This parameter modification reduces the pull-up control transistor's parasitic capacitance impact on the pull-up node, thereby improving circuit stability while maintaining standard manufacturing processes
2Reliability
If the channel length of the pull-up control transistor is reduced to minimize parasitic capacitance, then circuit stability improves, but the transistor's current driving capability may be affected
Solution Approach 1:
The patent applies local quality by creating asymmetric channel lengths between different transistors in the same gate drive unit. The pull-up control transistor has a locally optimized short channel length to minimize parasitic capacitance, while the scan signal output transistor maintains a longer channel length for sufficient current driving capability. This localized differentiation resolves the contradiction between stability and power
3Productivity
If the channel length ratio between pull-up control transistor and scan signal output transistor is optimized, then switching time is reduced and charging rate is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent establishes a specific parameter range for the channel length ratio (1:8 to 1:12) that balances switching performance and manufacturability. This quantified parameter specification enables manufacturers to achieve optimal switching speed while maintaining reasonable manufacturing precision tolerances
Data Source
AI summary
A gate drive circuit and a display panel. The gate drive circuit includes multi-stage cascaded gate drive units. The gate drive units each include a pull-up control module, an output module, a pull-down module, a pull-down maintain module, a first reference low-level signal input terminal, a second reference low-level signal input terminal, and a pull-up node located in a line between the pull-up control module and the output module. The pull-up control module includes a pull-up control transistor that is electrically connected to the pull-up node and configured to pull a potential of the pull-up node up. The output module includes a scan signal output transistor that is electrically connected to the pull-up node and configured to output a present-stage scan signal under control of the potential of the pull-up node.