Gate Drive Circuit With Waveform Inversion for Narrow-Bezel Displays
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Solution Overview
Problem
Current gate drive circuits face limitations in drive capability, requiring large thin-film transistors that increase the non-display area, and communication issues arise due to voltage mismatches between chips with different power supplies.
Innovation Solution
A gate drive circuit with shift registers and buffers that perform multiple waveform inversions to improve drive capability, reducing the need for large transistors and incorporating a level shifter for voltage compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If large thin-film transistors are used to improve drive capability, then the drive capability is enhanced, but the non-display area increases
Solution Approach 1:
The gate drive circuit is divided into multiple shift registers and buffers that work in cascade. Each stage processes the scanning signal sequentially, allowing the use of smaller transistors in each individual stage while maintaining overall drive capability through the cumulative effect of multiple stages.
Solution Approach 2:
The patent changes the waveform characteristics by performing multiple inversions on the scanning signal. This transforms the signal edges to be steeper and more controlled, improving the drive capability without requiring larger transistors. The parameter change focuses on signal timing and voltage transitions rather than transistor size.
2Adaptability or versatility
If chips with different power supplies are used, then device versatility is improved, but communication issues arise due to voltage mismatches
Solution Approach 1:
The patent introduces a level shifter circuit as an intermediary between chips with different power supplies. This level shifter converts voltage levels from one chip's power domain to another chip's power domain, enabling reliable communication between chips with different power supply voltages without direct voltage conflicts.
3Loss of time
If scanning signal edge times are reduced to improve charging time, then pixel charging adequacy is enhanced, but drive capability requirements increase
Solution Approach 1:
The patent performs multiple waveform inversions on the scanning signal in advance before it reaches the pixel circuit. This preliminary shaping of the signal creates steeper edges and more controlled transitions, so that when the signal finally charges the pixel capacitor, the charging process is more efficient and completes faster, reducing the required charging time.
Data Source
AI summary
Provided is a gate drive circuit, including a plurality of shift registers and buffers in cascade, wherein each of the shift registers is configured to output a first gate scanning signal stage by stage according to a preset scanning timing; and each of the buffers is configured to perform waveform inversion on the first gate scanning signal for a plurality of times to convert the first gate scanning signal into a second gate scanning signal, wherein falling edge time of the second gate scanning signal is less than falling edge time of the first gate scanning signal.