Gate Driver With Field-Adjustable UVLO
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Solution Overview
Problem
Gate driver circuits face challenges in miniaturization due to breakdown voltages and require separate designs for different semiconductor devices with varying voltage levels, leading to increased costs and complexity from the need for multiple UVLO voltage levels.
Innovation Solution
A gate driver system with a field-adjustable UVLO level that allows for adjustable UVLO settings without additional pins, using a resistor-based voltage divider to adjust the trigger point of the UVLO circuit, enabling the same gate driver to accommodate various semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate gate driver designs are created for different semiconductor devices with varying voltage levels, then each device can be optimized for its specific voltage requirements, but the number of designs and models increases leading to increased costs and complexity
Solution Approach 1:
The gate driver is designed with a universal UVLO circuit that can operate at multiple voltage levels by adjusting an external resistor, allowing a single design to serve multiple semiconductor devices with different voltage requirements. This eliminates the need for separate designs for each voltage level while maintaining optimized performance.
Solution Approach 2:
The UVLO trigger voltage is made adjustable by changing the resistance value of an external resistor connected to the ADJ pin. This parameter change allows the same gate driver circuit to adapt to different voltage levels (e.g., 12V, 15V, 18V) without requiring redesign, thus reducing the number of designs needed.
2Adaptability or versatility
If additional pins are added to the gate driver to enable adjustable UVLO levels, then field-adjustability is achieved, but the package size increases counteracting miniaturization efforts
Solution Approach 1:
The ADJ pin serves multiple functions: it is used for normal operation as a control input and simultaneously serves as the adjustment point for the UVLO circuit. This multi-functionality allows UVLO adjustability without requiring an additional dedicated pin, thus avoiding package size increase.
Solution Approach 2:
The UVLO adjustment function is merged with the existing ADJ pin functionality. The external resistor connects to the ADJ pin, combining the normal control function and UVLO adjustment function into a single pin, eliminating the need for separate pins and maintaining compact package size.
3Ease of manufacture
If internally fixed UVLO voltage levels are used, then the gate driver design is simplified, but different semiconductor devices requiring different voltage levels require separate gate driver models increasing costs
Solution Approach 1:
The UVLO voltage level is changed by modifying the resistance value of an external resistor connected to the ADJ pin. This simple parameter change allows the same simplified internal design to accommodate different voltage levels (12V, 15V, 18V, etc.) without requiring complex internal circuitry or multiple designs.
Solution Approach 2:
An external resistor serves as an intermediary element that allows the user to adjust the UVLO voltage level without modifying the internal gate driver circuitry. This intermediary component provides flexibility while keeping the internal design simple and unchanged.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides flexibility and reduces costs by allowing a single gate driver design to accommodate different semiconductor devices, eliminating the need for multiple designs and additional pins, thus enhancing miniaturization capabilities and reducing engineering complexity.
Implementation Method 1
using a resistor-based voltage divider to adjust the trigger point of the UVLO circuit
Data Source
AI summary
Systems and methods for gate driver with field-adjustable undervoltage lockout (UVLO) are disclosed. A gate driver system comprises a control circuit and a driver circuit. The driver circuit incorporates a field-adjustable UVLO, a control logic, and an inverter. The level of the field-adjustable UVLO is adjustable by an external circuit, which can be a resistor based voltage divider. By setting the UVLO level externally adjustable and by moving a reference ground to the external voltage divider, the gate driver system is able to implement gate control for various load without needing extra ground pin.


