Gate Driver Pull-Up Circuit With Auxiliary Capacitor for Stable Gate Pulses
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Solution Overview
Problem
Continuous stress on pull-up transistors in gate drivers of display panels can lead to improper gate pulse output, resulting in horizontal band-shaped defects in the display.
Innovation Solution
A display apparatus is designed with a pull-up transistor configured by two transistors connected between a clock line and a gate line, and an auxiliary capacitor connected to a floating node between these transistors, to stabilize the voltage and prevent leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a pull-up transistor is continuously stressed to maintain gate signal output, then the gate driver can continuously drive the gate line, but hot carrier stress accumulates causing delayed falling periods and horizontal band defects
Solution Approach 1:
The pull-up transistor is divided into two separate transistors (first pull-up transistor and second pull-up transistor) that operate alternately. This segmentation allows one transistor to work while the other rests, preventing continuous stress accumulation on a single transistor and eliminating horizontal band defects while maintaining continuous gate signal output capability.
2Device complexity
If a single pull-up transistor is used to simplify the circuit structure, then device complexity is reduced, but hot carrier stress causes delayed falling periods and display defects
Solution Approach 1:
The single pull-up transistor is segmented into two transistors that share the workload. Each transistor experiences stress for only half the duty cycle, significantly reducing hot carrier stress accumulation and preventing display defects while maintaining relatively simple circuit structure.
Solution Approach 2:
The two pull-up transistors operate in periodic alternation, with each transistor being activated for a specific period and then deactivated. This periodic operation allows stress to be distributed over time, reducing peak stress on individual transistors and preventing hot carrier-induced display defects.
3Device complexity
If the pull-up transistor operates without voltage supplementation, then device complexity is minimized, but hot carrier stress delays the falling period of gate pulses
Solution Approach 1:
A capacitor is connected to the floating node of the pull-up transistor to preliminarily store voltage. When the transistor switches off, the capacitor provides supplemental voltage to maintain the gate signal level, ensuring the falling edge occurs at the correct time and preventing display defects caused by delayed falling periods.
Solution Approach 2:
The capacitor acts as a voltage cushion that compensates for voltage drops caused by hot carrier stress. By storing energy in advance, the capacitor cushions against voltage fluctuations and ensures stable gate signal output timing, preventing display defects without adding complex voltage supply circuits.
Data Source
AI summary
A display apparatus is disclosed. An aspect of the present disclosure is directed to providing a display apparatus capable of supplying an auxiliary voltage to a floating node between first and second transistors configuring a pull-up transistor of a gate driver. The display apparatus may include a plurality of pixels connected to a gate line, and a stage configured to output a gate signal to the gate line, wherein the stage includes a pull-up transistor provided between a clock line configured to receive a gate clock and the gate line, the pull-up transistor includes a first transistor and a second transistor connected to each other, and an auxiliary capacitor is connected to a floating node between the first transistor and the second transistor.