Gate Driver Back-Gate Biasing for Low-Leakage Switching
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Solution Overview
Problem
Existing display devices face reliability issues due to the continuous turned-on state of always-on transistors, leading to increased leakage current and reduced efficiency in gate drivers.
Innovation Solution
The gate driver design incorporates a P-type transistor with a back gate receiving a variable or constant input voltage, allowing the threshold voltage to be negatively or positively shifted based on the gate signal's state, thereby reducing leakage current and improving reliability by ensuring quick turn-on/off of buffer transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an always-on transistor is continuously maintained in a turned-on state with a constant turn-on voltage applied to its gate, then the transistor remains protected and functional, but leakage current increases and reliability decreases
Solution Approach 1:
The patent applies the Dynamics principle by making the gate voltage of the always-on transistor variable rather than constant. The gate voltage dynamically switches between a first voltage level (during output period) and a second voltage level (during hold period), allowing the transistor to adapt its conductivity to operational requirements. This dynamic voltage control reduces leakage current during the hold period while maintaining proper functionality during the output period, thus resolving the contradiction between reliability and energy loss.
Solution Approach 2:
The patent implements Parameter changes by modifying the gate voltage parameter of the always-on transistor based on operational phase. During the output period, the gate voltage is set to a first level to ensure proper transistor operation and protection. During the hold period, the gate voltage is changed to a second level to minimize leakage current. This parameter adjustment strategy directly addresses the contradiction by optimizing the voltage parameter for different operational requirements.
2Reliability
If an always-on transistor is continuously turned on to protect other transistors, then protection function is maintained, but switching speed of buffer transistors decreases
Solution Approach 1:
The patent applies the Dynamics principle by dynamically controlling the gate voltage of the always-on transistor to enable rapid switching of buffer transistors. During the output period, the gate voltage is set to a first level that ensures the always-on transistor provides proper protection while allowing buffer transistors to switch quickly. During the hold period, the gate voltage is adjusted to a second level that maintains protection functionality while optimizing switching performance. This dynamic control resolves the contradiction between protection and switching speed.
Solution Approach 2:
The patent implements Periodic action by applying different gate voltages to the always-on transistor in periodic cycles corresponding to the output period and hold period. During the output period, a first gate voltage is applied to enable fast switching and proper protection. During the hold period, a second gate voltage is applied to maintain protection while optimizing for lower power consumption. This periodic voltage adjustment allows the system to alternate between optimization goals, resolving the contradiction between protection reliability and switching speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces leakage current in the always-on transistor during the hold period and ensures rapid switching in the output period, enhancing the overall reliability of the gate driver.
Implementation Method 1
a fourth transistor connected between the first control node and the second control node, the fourth transistor including a gate which receives the first low gate voltage or a low gate voltage higher or lower than the first low gate voltage and a back gate which receives an input voltage that is a variable voltage
Data Source
AI summary
In a gate driver that has first to nth stages including a kth stage, wherein k is a number between 1 and n, the kth stage includes a first transistor which transmits an input signal to a first control node, a fifth transistor including a gate connected to an inverting control node, a first terminal which receives a high gate voltage, and a second terminal connected to an output node, a sixth transistor including a gate connected to a second control node, a first terminal which receives a first low gate voltage or a clock signal, and a second terminal connected to the output node, and a fourth transistor connected between the first control node and the second control node, the fourth transistor including a gate which receives the first low gate voltage or a low gate voltage and a back gate which receives an input voltage.