Gate Driver Voltage Line Layout for Narrow OLED Bezel
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Solution Overview
Problem
The gate bezel area in organic light emitting display devices is enlarged due to the implementation of the gate driving circuit, which affects design and manufacturing efficiency.
Innovation Solution
A symmetrical structure is adopted for the output buffer block of the gate driving panel circuit, with gate low-potential voltage connection lines extended through the central area, and high-potential and low-potential voltage lines positioned on different sides of the gate driving circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the gate driving circuit is implemented in the display panel, then the gate driving function is achieved, but the gate bezel area increases
Solution Approach 1:
The patent applies dimensional change by transitioning from a planar arrangement of voltage lines to a three-dimensional stacked configuration. Multiple voltage lines (high-potential and low-potential) are arranged in different layers and positions around the gate driving circuit, utilizing vertical and spatial dimensions to reduce the horizontal footprint of the gate bezel area while maintaining all necessary electrical connections.
2Reliability
If voltage lines are arranged around the gate driving circuit, then electrical connections are established, but the gate bezel area is enlarged
Solution Approach 1:
The patent implements nesting by placing voltage lines in nested positions around the gate driving circuit. The high-potential voltage lines and low-potential voltage lines are arranged in concentric or adjacent layers, with connection lines extending through central areas to reach the gate driving circuit. This nested arrangement allows multiple electrical connections to be packed into a compact spatial configuration, reducing the overall gate bezel area while maintaining reliable electrical connectivity.
3Reliability
If multiple gate low-potential voltages with different levels are used, then voltage ripples are reduced, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by introducing multiple gate low-potential voltage lines with different voltage levels (e.g., first gate low-potential voltage and second gate low-potential voltage at different potentials). This parameter variation allows the system to reduce voltage ripples and improve signal stability by providing multiple voltage references, while the complexity is managed through systematic arrangement of these voltage lines around the gate driving circuit.
Data Source
AI summary
A display panel having a display area where a plurality of subpixels are disposed, a gate driving circuit disposed in a non-display area outside the display area to supply a plurality of scan signals to the plurality of subpixels, a plurality of gate high-potential voltage lines which are disposed in a side of the gate driving circuit for transferring a plurality of gate high-potential voltages, a plurality of gate low-potential voltage lines which are disposed in other side of the gate driving circuit for transferring a plurality of gate low-potential voltages, and a plurality of gate low-potential voltage connection lines which are extended through a central area of the gate driving circuit for transferring the plurality of gate low-potential voltages to the gate driving circuit.