Multi-Level Gate Driver Layout for Split-Screen Boundary Suppression

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The multi-level driving structure of gate drivers in display devices is prone to a partition refresh boundary split screen phenomenon due to large coupling capacitors causing insufficient high voltage at pixel compensation, resulting in dark displays.

Innovation Solution

A gate driver design with a plurality of levels, each including a driving circuit and a gating circuit, where the gate of the first switch in each level (except the first) is connected to the first node of the previous-level driving circuit, utilizing a pull-up module driven by this node voltage to reduce coupling and maintain high voltage output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a multi-level gate driver structure is used for partition refresh, then the display can be divided into multiple refresh zones, but the large coupling capacitor causes high voltage to be pulled down at partition boundaries, resulting in dark display

Engineering Contradiction:
Improvepartition refresh capabilityVSAvoiddisplay quality at partition boundary
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces a compensation capacitor connected between the high voltage node and the gating control signal node as an intermediary element. This compensation capacitor acts as a mediator to counterbalance the unwanted coupling effect of the large coupling capacitor, thereby preventing the high voltage pull-down phenomenon at partition boundaries while maintaining the multi-level partition refresh structure

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent modifies the electrical parameters at the partition boundary by introducing a compensation capacitor with specific capacitance value. This changes the voltage distribution characteristics and coupling effects at the critical partition boundary region, transforming the harmful voltage pull-down into a controlled compensation mechanism that maintains display quality

Inventive Principle:
Principle #35Parameter changes

2Ease of operation

If a large coupling capacitor is used in the gating circuit, then the gating control signal can be effectively coupled, but the high voltage output is pulled down when the gating control signal hops, causing insufficient pixel compensation

Engineering Contradiction:
Improvegating control signal couplingVSAvoidhigh voltage output stability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The compensation capacitor serves as an intermediary component that decouples the harmful interaction between the gating control signal transitions and the high voltage output. By introducing this intermediate capacitive element, the patent enables the large coupling capacitor to function for signal coupling while the compensation capacitor counteracts its unwanted voltage pull-down effect on the high voltage node

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent converts the harmful effect of the large coupling capacitor (which causes high voltage pull-down) into a beneficial compensation mechanism. By intentionally introducing a compensation capacitor with opposite polarity effect, the harmful voltage drop is transformed into a compensated signal that maintains proper high voltage levels during gating transitions

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS20260073827A1Gate driver, display panel and display device
Publication Date: 2026.03.12 XIAMEN TIANMA DISPLAY TECH CO LTD
  • US20260073827A1 patent drawing
  • US20260073827A1 patent drawing
  • US20260073827A1 patent drawing

AI summary

The present disclosure provides a gate driver, a display panel and a display device. The gate driver includes a plurality of levels that sequentially output a gate control signal through a gate control line. Each level includes a driving circuit and a gating circuit, where the driving circuit includes a pull-up module; the gating circuit includes a gating control signal writing module, and the gating control signal writing module includes a first switch. The gate of the first switch in each level, except the first level of the plurality of levels, is connected to a first node of a previous-level driving circuit, and the voltage of the first node is configured to drive the pull-up module.