Gate Driver Capacitor Configuration for Signal Rising Speed
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Solution Overview
Problem
In display devices, the deterioration of buffer transistors leads to a slowdown in the rising speed of output gate signals, resulting in decreased boosting and output performance due to a vicious cycle of slowed Q node and gate signal rising speeds.
Innovation Solution
The implementation of capacitors connected between the gate electrode of pull-up transistors and output nodes, as well as between output nodes and low-potential voltage lines, to maintain the rising speed of gate signals and reduce output losses by enhancing the output characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If capacitors are connected between the gate electrode of pull-up transistors and output nodes, then the rising speed of gate signals is maintained, but the device complexity increases
Solution Approach 1:
The capacitor is connected in advance between the gate electrode of the pull-up transistor and the output node to prepare for maintaining the rising speed of the gate signal. This preliminary configuration ensures that when the pull-up transistor operates, the capacitor is already in position to supply additional charge and maintain the signal rising speed, even as the transistor deteriorates over time.
Solution Approach 2:
The capacitor acts as a cushioning element that compensates for the deterioration of the pull-up transistor. By placing the capacitor beforehand, it provides a buffer that maintains the gate signal rising speed despite the gradual degradation of the transistor's performance, preventing the vicious cycle of slowed signal propagation.
2Loss of energy
If capacitors are connected between output nodes and low-potential voltage lines, then output losses are reduced, but the device complexity increases
Solution Approach 1:
The capacitor is connected in advance between the output node and the low-potential voltage line to prepare for reducing output losses. This preliminary configuration ensures that the capacitor is ready to supply additional charge when needed, minimizing energy loss at the output stage.
Solution Approach 2:
The capacitor serves as a cushioning element that compensates for energy loss at the output node. By placing the capacitor beforehand, it provides a buffer that maintains output signal strength and reduces energy dissipation, even as the circuit operates and components deteriorate.
3Productivity
If pull-up transistors are used to output gate signals, then the gate signals can be generated, but the rising speed slows down due to transistor deterioration
Solution Approach 1:
The capacitor is connected in advance between the gate electrode of the pull-up transistor and the output node to prepare for maintaining the rising speed. This preliminary configuration ensures that the capacitor is ready to supply additional charge when the transistor operates, compensating for the transistor's deterioration and maintaining signal integrity.
Solution Approach 2:
The capacitor acts as a cushioning element that compensates for the pull-up transistor's deterioration. By placing the capacitor beforehand, it provides a buffer that maintains the gate signal rising speed despite the gradual degradation of the transistor's performance, preventing the vicious cycle of slowed signal propagation.
Data Source
AI summary
A gate driver according to an embodiment and a display device using the same are disclosed. The gate driver includes a plurality of signal transmitters, wherein an nth signal transmitter includes, a (1-1)th output circuit configured to output a carry signal to a first output node according to a voltage of a first control node and a voltage of a second control node, a (1-2)th output circuit configured to output a boosting signal to a second output node according to a voltage of the first control node and a voltage of the second control node, wherein the (1-2)th output circuit includes a pull-up transistor configured to apply a gate high voltage to the first output node, a pull-down transistor configured to apply a gate low voltage to the first output node, and a first capacitor connected between a gate of the pull-up transistor and the second output node.