Gate Driver Carry Boost Circuit for Short DLG Pulses
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Solution Overview
Problem
The Dual Line Gate (DLG) mode in display devices reduces the period of activation pulses for gate and carry signals, leading to insufficient charging of transistor voltages and decreased reliability of gate and carry signals, which affects display quality.
Innovation Solution
A gate driver with specific circuit configurations, including CQ node charging circuits, QB node control circuits, and carry output circuits, utilizes transistors and capacitors to boost and manage signal voltages, ensuring adequate charging even with shortened activation pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the DLG mode simultaneously drives two consecutive gate lines, then the driving frequency increases from 60 Hz to 120 Hz, but the period of activation pulses decreases by half causing insufficient voltage charging
Solution Approach 1:
The patent applies preliminary action by charging the CQ node to a second high gate voltage (higher than conventional high gate voltage) in advance before the activation pulse arrives. This pre-charging ensures that when the shortened activation pulse occurs in DLG mode, the transistor gate electrode already has sufficient voltage headroom to maintain reliable switching despite the reduced pulse width.
Solution Approach 2:
The patent changes the voltage parameter by introducing a second high gate voltage that is higher than the conventional high gate voltage. This voltage parameter change allows the transistor to achieve full channel formation and saturation more quickly, enabling reliable operation with the shortened activation pulses in DLG mode while maintaining high driving frequency.
2Productivity
If the activation pulse period decreases in DLG mode, then the driving frequency increases, but the reliability of gate signal and carry signal decreases
Solution Approach 1:
The patent applies preliminary action by pre-charging the CQ node to a second high gate voltage before the activation pulse arrives. This ensures that even with the shortened pulse period in DLG mode, the transistor has sufficient voltage margin to maintain reliable switching and signal integrity, thus preserving signal reliability while achieving high driving frequency.
Solution Approach 2:
The patent provides beforehand cushioning by maintaining the CQ node at a second high gate voltage (higher than conventional high gate voltage) as a voltage cushion. This voltage cushion compensates for the reduced charging time caused by shorter activation pulses in DLG mode, ensuring that the transistor gate electrode maintains adequate voltage throughout the shortened pulse duration to preserve signal reliability.
3Productivity
If the activation pulse period is shortened, then the driving frequency increases, but the display quality decreases
Solution Approach 1:
The patent applies preliminary action by pre-charging the CQ node to a second high gate voltage before the activation pulse arrives. This ensures that transistors maintain proper switching characteristics and voltage levels throughout the shortened pulse period in DLG mode, preventing display artifacts and maintaining high display quality even at increased driving frequencies.
Solution Approach 2:
The patent changes the voltage parameter by introducing a second high gate voltage higher than conventional high gate voltage. This voltage parameter change ensures that transistors maintain adequate channel formation and switching performance during the shortened activation pulses in DLG mode, thereby preserving display quality while achieving higher driving frequencies.
Data Source
AI summary
A carry output circuit includes a carry variable on transistor, a thirteenth transistor, a fourteenth transistor, and a carry boost capacitor, wherein the carry variable on transistor includes a gate electrode connected to a CQS node, a first electrode connected to a CQ node, and a second electrode connected to a carry Q node, the thirteenth transistor includes a gate electrode connected to a carry Q node, a first electrode receiving the carry clock signal, and a second electrode connected to a carry node, the fourteenth transistor includes a gate electrode connected to the QB node, a first electrode receiving the second low gate voltage, and a second electrode connected to the carry node, and the carry boost capacitor includes a first electrode connected to the carry Q node and a second electrode connected to the carry node.