Gate Driver Shift Registers for Non-Overlapped Charge-Sharing Pixels
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Solution Overview
Problem
Conventional gate driving circuits for display panels with charge sharing pixel structures face challenges in generating non-overlapped main and sub gate driving signals, leading to complex circuit structures and layouts, which increase costs and reduce efficiency.
Innovation Solution
A gate driving circuit with multiple shift registers that utilize multi-phase clock signals to generate non-overlapped main and sub gate driving signals, where each shift register includes a driving unit, pull-up, and pull-down units controlled by specific clock signals, ensuring that the signals are phase-advanced or phase-delayed to avoid overlap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate driving circuits are used to generate non-overlapped main and sub gate driving signals, then the charge sharing pixel structure can operate, but the circuit structure becomes complex and layout becomes complicated
Solution Approach 1:
The gate driving circuit is divided into multiple independent shift registers (first shift register for main gate signal, second shift register for sub gate signal). Each shift register independently generates one type of gate driving signal, segmenting the complex signal generation task into simpler, manageable units that can be designed and laid out separately, thus reducing overall circuit complexity
Solution Approach 2:
The patent introduces multi-phase clock signals (at least three phases) to control the timing of different shift registers. By adding the time dimension with phased clock signals, the circuit achieves non-overlapped signal generation without increasing spatial complexity, as the timing control occurs in the temporal dimension rather than requiring additional complex spatial arrangements
2Reliability
If conventional gate driving circuits with complex structure are used, then non-overlapped signals can be generated, but manufacturing cost increases
Solution Approach 1:
By segmenting the gate driving function into separate shift registers for main and sub signals, each module can be manufactured using standard, well-established processes. This modular approach allows for easier manufacturing and testing compared to a monolithic complex circuit, potentially reducing manufacturing costs through standardized production techniques
Solution Approach 2:
The use of periodic multi-phase clock signals provides a regular, predictable timing mechanism that simplifies the manufacturing process. The periodic nature of the clock signals allows for consistent signal generation and easier quality control during manufacturing, reducing the need for complex adjustments and lowering overall manufacturing costs
3Reliability
If conventional gate driving circuits are used, then charge sharing can be achieved, but circuit layout becomes complicated
Solution Approach 1:
The circuit layout is segmented into distinct regions for the first shift register (main gate signal) and second shift register (sub gate signal). This spatial segmentation simplifies the layout process by clearly defining functional zones, making it easier to route connections and manage signal paths without complex interconnections
Solution Approach 2:
The patent resolves layout complexity by moving the differentiation between main and sub gate signals into the time dimension through phased clock signals. Instead of requiring complex spatial arrangements to ensure non-overlapping signals, the solution uses temporal separation with phased clocks, allowing for simpler, more regular spatial layout of the circuit components
Data Source
AI summary
The disclosure provides a gate driving circuit on array applied to a display panel with charge sharing pixel structure. In particular, the gate driving circuit is adapted to receive multi-phase clock signal and includes a plurality of shift registers. Each shift register includes a driving circuit including a first driving transistor and a second driving transistor, a pull-down unit and at least one pull-up unit, so that is capable of generating mutually non-overlapped main gate driving signal and sub gate driving signal. Furthermore, the advantage of the disclosure is to provide a gate driving circuit with simplified circuit structure and circuit layout.