Gate Driver Circuit for Display Devices with Scan Pulse Distortion
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Solution Overview
Problem
In LCD devices with increased display areas, the longer gate lines result in increased resistance and capacitance, causing distortion of scan pulses, which shortens the effective charging time and reduces the duration of the data voltage supplied to pixel electrodes, leading to insufficient charging of pixel electrodes.
Innovation Solution
A driving circuit with two shift registers that sequentially supply scan pulses to both ends of the gate lines, allowing each stage to drive adjacent lines for a predetermined period, thereby increasing the effective charging time by overlapping successive scan pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate line length is increased to cover larger display areas, then the display area is improved, but the resistance and capacitance of the gate line increase causing scan pulse distortion
Solution Approach 1:
The gate driver is divided into multiple stages (first stage AST1, second stage AST2, etc.) that sequentially output scan pulses to different gate lines. Each stage acts as an independent unit that can be optimized for its specific gate line, allowing the system to handle long gate lines without compromising pulse quality across the entire display.
Solution Approach 2:
The scan pulse output from one stage is used to preliminarily charge the gate line before the main scanning action. The gate line is pre-charged to a first voltage level, then subsequently charged to a second voltage level, ensuring sufficient charging time even for long gate lines with high resistance and capacitance.
2Area of stationary object
If the gate line length is increased, then the display area is improved, but the effective charging time for pixel electrodes is shortened
Solution Approach 1:
The gate line is pre-charged to a first voltage level before the main scanning action. This preliminary charging action ensures that when the main scan pulse arrives, the gate line is already partially charged, extending the effective charging time for pixel electrodes even in large display areas with long gate lines.
Solution Approach 2:
The scanning process uses continuous overlapping of scan pulses from multiple stages. While one stage is charging its gate line, the previous stage is already discharging, and the next stage is preparing its pulse. This continuous action ensures uninterrupted charging of pixel electrodes throughout the scanning process.
3Duration of action of moving object
If scan pulses are output sequentially from multiple stages, then the gate lines can be driven with sufficient pulse width, but the device complexity increases
Solution Approach 1:
The shift register is segmented into multiple identical stages (AST1, AST2, etc.) that can be implemented using standard circuit cells. Each stage is a simple unit that receives clock signals and outputs scan pulses sequentially. This segmentation allows complex functionality to be achieved through repetition of simple, well-understood circuit blocks.
Solution Approach 2:
Each stage of the shift register serves multiple functions: it generates scan pulses for its associated gate line, provides clock signal distribution, and enables sequential scanning across all gate lines. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in overall device complexity.
Data Source
AI summary
A driving circuit of a display device and a method for driving the display device are disclosed which are capable of reducing distortion of scan pulses supplied to gate lines of a liquid crystal panel. The driving circuit includes a first shift register for sequentially supplying first scan pulses to one-side ends of gate lines included in a display, respectively, to sequentially drive the gate lines, the first shift register simultaneously driving at least two adjacent ones of the gate lines for a predetermined period of time, and a second shift register for sequentially supplying second scan pulses to the other-side ends of the gate lines, respectively, to sequentially drive the gate lines, the second shift register simultaneously driving at least two adjacent ones of the gate lines for a predetermined period of time.