Gate Driver Circuit for Narrow Bezel OLED Displays
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Solution Overview
Problem
Existing gate driver circuits for OLED displays face challenges in efficiently outputting gate signals to any line during a progressive scan process, leading to increased bezel size and limitations in implementing a narrow bezel design due to the need for inverter circuits and fixed clock timing.
Innovation Solution
A gate driver circuit with a configuration that includes transistors to generate independent line control signals, allowing for flexible output of gate signals to any line, and an edge trigger circuit that can generate gate-on and gate-off voltages based on node voltages, enabling phase changes and holding gate signals irrespective of the input signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If inverter circuits are used to output gate signals to any line during progressive scan, then the gate signal output flexibility is improved, but the bezel size increases
Solution Approach 1:
The patent extracts and removes the inverter circuits from the gate driver circuitry. By using a different circuit configuration that directly outputs the necessary gate signals without requiring inversion operations, the bezel area is reduced while maintaining the ability to output gate signals to any line during progressive scan mode.
Solution Approach 2:
Instead of using inverter circuits to achieve signal inversion, the patent employs an alternative approach by configuring the gate driver circuit to directly generate the required gate signal waveforms through a different circuit topology, thereby eliminating the need for separate inverter components.
2Device complexity
If fixed clock timing is used in the gate driver circuit, then the circuit design is simplified, but the ability to sense electrical characteristics of subpixels in real-time is limited
Solution Approach 1:
The patent implements dynamic clock timing control where the clock signal timing can be adjusted based on the sensing requirements. The gate driver circuit is configured to modify clock timing dynamically during different operating modes (display mode vs. sensing mode), enabling real-time electrical characteristic sensing of subpixels while maintaining operational flexibility.
3Device complexity
If the gate driver circuit is configured for progressive scan with fixed timing, then the scanning process is simplified, but the efficiency of line scanning and subpixel sensing is reduced
Solution Approach 1:
The patent implements dynamic timing control in the gate driver circuit, allowing the scanning process to adapt its timing parameters based on operational requirements. During sensing operations, the circuit can adjust timing to optimize the sequence for electrical characteristic measurement, thereby improving scanning efficiency without significantly increasing overall system complexity.
Data Source
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AI summary
A gate driver circuit, a display device, and a method of driving the display device are disclosed. The gate driver circuit includes a first transistor supplying a start signal to a Q node in response to a clock, a second transistor adjusting a gate voltage of the first transistor in response to the clock, a third transistor adjusting a gate voltage of the second transistor in response to the start signal, a fourth transistor changing a voltage of a QB node, a fifth transistor switching a current path between the first transistor and the Q node in response to a first line control signal, a sixth transistor supplying a gate-off voltage to an output node, a seventh transistor supplying a gate-on voltage to the output node, and an eighth transistor supplying a second line control signal to the QB node.