Gate Driver Circuit Uniformity via Stage Segmentation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Display devices experience deteriorated image quality due to output differences between gate signals, leading to variations in image display across different lines, which are caused by non-uniform magnitudes and time durations of gate signals supplied to gate lines.

Innovation Solution

A gate driver circuit is designed with multiple stage circuits, each including M, Q, QH, and QB nodes, along with specific modules like line selectors, stabilizers, inverters, and signal output modules, to manage voltage levels and timing of gate signals, ensuring uniformity and reducing output differences between gate signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If gate signals are supplied to multiple gate lines using conventional driver circuits, then the display device can operate with multiple scanning lines, but output differences between gate signals occur causing non-uniform voltage magnitudes and time durations across different lines

Engineering Contradiction:
Improvemulti-line scanning capabilityVSAvoidgate signal uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The gate driver circuit is divided into multiple stage circuits (first stage circuit, second stage circuit, etc.), where each stage circuit is responsible for generating gate signals for specific gate lines. This segmentation allows independent optimization and control of each stage to ensure uniform output characteristics across all gate lines while maintaining multi-line scanning capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit employs feedback mechanisms through interconnected nodes (M node, Q node, QH node, QB node) and control modules that monitor and adjust the output gate signals. The feedback loops ensure that voltage magnitudes and time durations remain uniform across different gate lines by dynamically compensating for variations in real-time.

Inventive Principle:
Principle #23Feedback

2Manufacturing precision

If complex stage circuits with multiple nodes and stabilizers are implemented, then gate signal uniformity is improved, but device complexity increases

Engineering Contradiction:
Improvegate signal uniformityVSAvoidcircuit structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Multiple functional modules (line selector, stabilizers, inverters, output modules) are merged into integrated stage circuits that share common nodes (M, Q, QH, QB nodes). This merging reduces the overall number of discrete components and interconnections while maintaining the precision control needed for uniform gate signal output across multiple gate lines.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Each stage circuit is designed as a universal module capable of generating gate signals for multiple gate lines with consistent characteristics. The multi-functional design allows the same circuit architecture to be replicated across different stages, simplifying manufacturing and reducing design complexity while ensuring uniformity through standardized performance parameters.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11482179B2Gate driver circuit and display device including the same
Publication Date: 2022.10.25 LG DISPLAY CO LTD
  • US11482179B2 patent drawing
  • US11482179B2 patent drawing
  • US11482179B2 patent drawing

AI summary

A gate driver circuit includes a plurality of stage circuits, each stage circuit supplies a gate signal to each of gate lines arranged in a display panel and includes a M node, a Q node, a QH node, and a QB node, and each stage circuit includes a line selector, a Q node controller, a Q node and QH node stabilizer, an inverter, a QB node stabilizer, a carry signal output module, and a gate signal output module, and a high voltage level period of a carry clock signal is set not to overlap with a high voltage level period of a first scan clock signal.